Digital Equipment Corporation Digital Semiconductor 21164 Alpha Microprocessor User's Guide

Digital Semiconductor 21164 AlphaMicroprocessor Evaluation BoardUser’s GuideOrder Number: EC–QD2UD–TERevision/Update Information: This document supers

and peripheral component interconnect (PCI) and Industry StandardArchitecture (ISA) devices.• Chapter 4, System Address Mapping, describes the mapping

A.2 PCI Sparse I/O SpaceA.2.1.5 Configuration Jumpers (CONF4—CONF15)Reading the addresses listed in Table A–5 returns the value of theconfiguration jump

A.2 PCI Sparse I/O SpaceTable A–7 SIO PCI-to-ISA Bridge Operating Register Address Space MapOffset Address Register000 85.C000.0000 DMA1 CH0 Base and

A.2 PCI Sparse I/O SpaceTable A–7 (Cont.) SIO PCI-to-ISA Bridge Operating Register Address SpaceMapOffset Address Register083 85.C000.1060 DMA Channel

A.2 PCI Sparse I/O SpaceTable A–7 (Cont.) SIO PCI-to-ISA Bridge Operating Register Address SpaceMapOffset Address Register0C6 85.C000.18C0 DMA2 CH1 Ba

A.2 PCI Sparse I/O SpaceTable A–7 (Cont.) SIO PCI-to-ISA Bridge Operating Register Address SpaceMapOffset Address Register41B 85.C000.8360 CH3 Scatter

A.3 PCI Dense Memory SpaceA.3 PCI Dense Memory SpacePCI dense memory space occupies physical addresses 86.0000.0000 through86.FFFF.FFFF and is typical

A.3 PCI Dense Memory SpaceA.3.3 Flash ROM Configuration RegistersTable A–10 lists the configuration registers for the Intel 28F008SA 1MB flashROM. A read

A.3 PCI Dense Memory SpaceTable A–10 Flash ROM Configuration RegistersOffsetData Written onFirst Access RegisterX1FF Read array/reset registerX 90 Inte

A.4 PCI Configuration Address SpaceA.4 PCI Configuration Address SpaceThe PCI configuration address space occupies physical addresses 87.0000.0000through

A.4 PCI Configuration Address SpaceTable A–12 SIO PCI-to-ISA Bridge Configuration Address Space MapOffset Address Register00–01 87.0008.0008 Vendor ID02

Data UnitsThe following data unit terminology, common within Digital, is used throughoutthis guide:Term Words Bytes BitsWord 1 2 16Longword 2 4 32Quad

A.5 PCI Interrupt Acknowledge/Special Cycle Address SpaceA.5 PCI Interrupt Acknowledge/Special Cycle Address SpaceThis space occupies physical address

A.6 Hardware-Specific and Miscellaneous Register SpaceTable A–13 (Cont.) CIA Control, Diagnostic, and Error RegistersRegister Type Address DescriptionC

A.6 Hardware-Specific and Miscellaneous Register SpaceA.6.3 CIA PCI Address Translation Map SpaceCIA PCI address translation map space occupies physica

A.6 Hardware-Specific and Miscellaneous Register SpaceTable A–15 (Cont.) PCI Address Translation RegistersRegister Type Address DescriptionTB0_PAGE2 RW

A.6 Hardware-Specific and Miscellaneous Register SpaceTable A–15 (Cont.) PCI Address Translation RegistersRegister Type Address DescriptionTB7_PAGE3 RW

BSROM InitializationThe 21164 Alpha microprocessor provides a mechanism for loading the initialinstruction stream (Istream) from a compact serial ROM

B.1 SROM Initialization9. Scan the system flash ROM for a special header that specifies where andhow the system flash ROM firmware should be loaded.10. Co

B.2 Firmware InterfaceTable B–1 (Cont.) Output Parameter DescriptionsOutput Parameter Parameter Descriptionr18 (a2)—Cycle count inpicosecondsThis valu

B.2 Firmware InterfaceTable B–1 (Cont.) Output Parameter DescriptionsOutput Parameter Parameter Descriptionr21 (a5)—System contextvalueThe context val

B.4 CPU Bus Interface TimingTable B–3 Typical SRAM SpecificationsFunction DescriptionToe Access from OE valid to data validTwc Write cycle timeTwp Writ

– An UNPREDICTABLE result might acquire an arbitrary value subjectto a few constraints. Such a result might be an arbitrary function ofthe input opera

B.5 Bcache Read and Write Timing CalculationsB.5 Bcache Read and Write Timing CalculationsThe following sections describe methods of calculating read

B.5 Bcache Read and Write Timing CalculationsOnce the index signals have reached the SRAMs and the write-enable hasbeen asserted, it must be determine

B.5 Bcache Read and Write Timing CalculationsB.5.3 Read/Write Spacing CalculationsThe 21164 uses the RD_WR_SPC field as the number of CPU cycles to ins

B.8 Special ROM HeaderB.8 Special ROM HeaderThe MAKEROM tool is used to place a special header on ROM image files. TheSROM allows the system (flash) ROM

B.8 Special ROM HeaderTable B–5 describes each entry in the special header.Table B–5 Special Header Entry DescriptionsEntry DescriptionValidation and

B.8 Special ROM HeaderTable B–5 (Cont.) Special Header Entry DescriptionsEntry DescriptionFirmware ID The firmware ID is a byte that specifies the firmwa

B.9 Flash ROM StructureB.9 Flash ROM StructureDuring the power-up and initialization sequence, the EB164 always loads thefirst image if BOOT_OPTION=1 (

B.9 Flash ROM StructureChanging TOY RAM Location 3F—Basic Debug Monitor CommandsFollow this procedure to change the value in location 0x3F, then load

B.9 Flash ROM StructureChanging TOY RAM Location 0x3F—Debug MonitorbootoptCommandUse the debug monitorbootoptcommand to change the value in location 3

B.10 Flash ROM AccessB.10 Flash ROM AccessThe flash ROM can be viewed as two banks of 512KB each. At power-upthe lower 512KB bank is accessed using the

Data Field SizeThe term INTnn, where nn is one of 2, 4, 8, 16, 32, or 64, refers to a data fieldof nn contiguous NATURALLY ALIGNED bytes. For example,

B.11 Icache Flush CodeB.11 Icache Flush CodeThe following code is loaded into memory after the system ROM image. Thecode is then executed to flush the

CTechnical Support and OrderingInformationC.1 Obtaining Technical SupportIf you need technical support or help deciding which literature best meets yo

C.2 Ordering Digital Semiconductor ProductsProduct Order NumberDigital Semiconductor 21164 266-MHz Alpha Microprocessor 21164–266Digital Semiconductor

C.3 Ordering Digital Semiconductor LiteratureC.3 Ordering Digital Semiconductor LiteratureThe following table lists some of the available Digital Semi

C.4 Ordering Third-Party LiteratureC.4 Ordering Third-Party LiteratureYou can order the following third-party literature directly from the vendor:Titl

GlossaryThis glossary provides definitions for terms and acronyms associated with theEB164 and chips, specifically as applied to Alpha architecture.ASIC

cache for data, and one unified 96KB L2 combined instruction and data cache.See also Bcache and write-back cache.CASColumn address strobe.CIAControl, I

ISAIndustry Standard Architecture. An 8-bit or 16-bit interface for interconnectingdata storage, data processing, and peripheral control devices in a

RASRow address strobe.regionOne of four areas in physical memory space based on the two most significant,implemented, physical address bits.RISCReduced

write-back cacheA cache in which copies are kept of any data in the region. Read and writeoperations may use the copies, and write operations use addi

Index21171See CIA chip or DSW chip21171-BASee DSW chip21171-CASee CIA chip21171 chipset, 1–3, 3–4See also CIA chip See also DSW chip64-byte mode, 3–3A

CCacheSee also BcacheSIMM connectors, 2–10Chipset overview, 3–4Chipset support, 1–3CIA chip, 3–4Clockfrequency multiplier, 3–16Clock divisor jumper, 2

Functional description (cont’d)interrupts, 3–13 to 3–15ISA bus devices, 3–8 to 3–12main memory interface, 3–6 to 3–7PCI devices, 3–7 to 3–8reset and i

PParallel port connector, 2–11Partsordering, C–1PC87312 register address map, A–2PCIbus connectors, 2–10configuration address space, A–16dense memory s

System softwaresoftware support, 1–5TTechnical support, C–1Test SROM port, 3–21Third-party documentation, C–4Time-of-year clock, 3–11Timing, 3–16UUbus

1Introduction to the EB164This chapter provides an overview of the EB164, its components, features, anduses.The Digital Semiconductor 21164 Alpha Micr

1.1 System Components and FeaturesFigure 1–1 EB164 Functional Block Diagram21164 AlphaMicroprocessorIndex21171−BAData Switch(X4)21171−CAControl, I/O I

1.1 System Components and Features1.1.1 Digital Semiconductor 21171 Core Logic ChipsetThe 21164 is supported by the 21171 chipset. The chipset consist

1.1 System Components and Featuresmost cases. The Bcache size can be reconfigured through onboard hardwarejumpers. As implemented in the EB164, the Bca

1.1 System Components and FeaturesA Xilinx XC17128 serial ROM (SROM) contains initial code that is loadedinto the 21164 instruction cache (Icache) on

March 1996Possession, use, or copying of the software described in this publication is authorized onlypursuant to a valid written license from Digital

1.1 System Components and Features1.1.8 Design SupportThe full database, including schematics and source files, is supplied. Userdocumentation is also

2System Configuration and ConnectorsThe EB164 uses jumpers to implement configuration parameters suchas variations in backup cache (Bcache) size, access

2.1 Configuration JumpersFigure 2–1 EB164 Jumper LocationsMK−2306−3011J11J14J17J16J1512–2 System Configuration and Connectors

2.1 Configuration JumpersFigure 2–2 Configuration JumpersJ1irq3123index22index21index20J17J16J15MK−2306−04BC_SIZE<2>BC_SIZE<1>BC_SIZE<0&g

2.1 Configuration JumpersTable 2–1 Configuration Jumper Position DescriptionsFeature Jack/Jumper—Pins and DescriptionSystem clockdivisorJ1—1/2, —3/4, —5

2.1 Configuration JumpersTable 2–1 (Cont.) Configuration Jumper Position DescriptionsFeature Jack/Jumper—Pins and DescriptionBC_SIZE<2:0> J1—11/12

2.1 Configuration JumpersTable 2–1 (Cont.) Configuration Jumper Position DescriptionsFeature Jack/Jumper—Pins and DescriptionBC_SPEED<2:0> J1—17/1

2.1 Configuration JumpersTable 2–1 (Cont.) Configuration Jumper Position DescriptionsFeature Jack/Jumper—Pins and DescriptionBOOT_OPTION J1—25/26 (CONF1

2.2 EB164 Connectors2.2 EB164 ConnectorsFigure 2–3 shows the EB164 connectors and Table 2–2 describes them.Figure 2–4 provides a detail of header conn

2.2 EB164 ConnectorsFigure 2–4 Detail of Header Connector J2J2Ground Pins:MK−2306−27A1357911131517192123255, 8, 9, 12, 13, 16,18, 22, and 25+12−V Pins

ContentsAbout This Guide ... ix1 Introduction to the EB1641.1 System Components and Features...

2.2 EB164 ConnectorsTable 2–2 EB164 Connector DescriptionsConnector Pins DescriptionMain Memory/Bcache SIMMSJ10 72 DRAM 0 SIMM (eb164.18)J9 72 DRAM 1

2.2 EB164 ConnectorsTable 2–2 (Cont.) EB164 Connector DescriptionsConnector Pins DescriptionMouse ConnectorJ34 6 Mouse connector (eb164.32)National 87

2.2 EB164 ConnectorsTable 2–2 (Cont.) EB164 Connector DescriptionsConnector Pins DescriptionSpeakerJ2—19/21/23/25 — Speaker connector pins (eb164.37)P

2.2 EB164 ConnectorsTable 2–2 (Cont.) EB164 Connector DescriptionsConnector Pins DescriptionPower ConnectorsJ18 12 Board power connector (eb164.40)Pin

2.2 EB164 ConnectorsTable 2–2 (Cont.) EB164 Connector DescriptionsConnector Pins DescriptionJ29 12 Board power connector (eb164.40)Pin Voltage/Signal1

3Functional DescriptionThis chapter describes the functional operation of the EB164. The descriptionintroduces the Digital Semiconductor 21171 ASIC su

3.1 EB164 Bcache Interface3.1 EB164 Bcache InterfaceThe 21164 controls the backup cache (Bcache) array (see Figure 3–1). Thedata bus (data<127:0>

3.1 EB164 Bcache InterfaceThe Bcache interface supports multiple cache sizes and access times. Thecache sizes supported are:• 2MB with Alpha cache sin

3.2 Digital Semiconductor 21171 Chipset3.2 Digital Semiconductor 21171 ChipsetThe 21171 chipset provides a cost-competitive solution for designers usi

3.2 Digital Semiconductor 21171 ChipsetFigure 3–2 Main Memory Interfacedata<127:0>Data Switch(X 4)Control, I/O Interface,Main Memory ArrayDRAM0D

3.5.3 Time-of-Year Clock . ... 3–113.5.4 Utility Bus Memory Device . . ... 3–123.5.5 ISA Expansion S

3.2 Digital Semiconductor 21171 ChipsetTwo DMA conversion methods are supported: direct mapping, where a baseoffset is concatenated with the PCI addre

3.3 Main Memory Interface• 2MB 36-bit DRAM SIMM• 4MB 36-bit DRAM SIMM• 8MB 36-bit DRAM SIMM• 16MB 36-bit DRAM SIMMThe following memory sizes are suppo

3.4 PCI Devices3.4.1 Saturn-IO (SIO) ChipTo provide the EB164 with greater flexibility, the only embedded PCI device isthe SIO PCI-to-ISA chip. All oth

3.5 ISA Bus DevicesFigure 3–3 ISA DevicesJ27J26J33J31PCI Busla<23:17>sd<15:0>PCI−to−ISABridge82378ZBsd<7:0>DisketteParallelCom1Com2C

3.5 ISA Bus Devices3.5.1 Combination ControllerThe EB164 uses the National Semiconductor PC87312 as the combinationcontroller chip. (See Figure 3–3.)

3.5 ISA Bus Devices3.5.2 Keyboard and Mouse ControllerThe Intel N8242 located on the ISA utility bus provides the keyboard andmouse controller functio

3.5 ISA Bus Devices3.5.4 Utility Bus Memory DeviceThe EB164 utility bus (Ubus) drives a flash ROM memory device. The flashROM chip provides 1MB of flash

3.6 Interrupts3.6 InterruptsThis section describes the EB164 interrupt logic. PCI-, ISA-, andCIA-generated interrupts are each described. Figure 3–4 s

3.6 InterruptsFigure 3–4 Interrupt LogicPCI Bus21164eb164.2cpu_reset_lKeyboardand MouseControllerISAPCI−to−ISABridgeCombinationControllerirq<15:3 ,

3.6 InterruptsTable 3–3 PCI-to-ISA SIO Bridge InterruptsPriority Label Controller Internal/External Interrupt Source1 IRQ0 1 Internal Internal timer 1

A I/O Space Address MapsA.1 PCI Sparse Memory Space . . . ... A–1A.2 PCI Sparse I/O Space ... A

3.7 System Clocks3.7 System ClocksFigure 3–5 shows the EB164 clock generation and distribution scheme.The EB164 system includes input clocks to the mi

3.7 System ClocksFigure 3–5 System Clocks and Distribution21164eb164.282378Bridgeeb164.25osc14osc2487312Combinationeb164.27sysclkclkbclkb_lkbclkmsclk8

3.7 System ClocksAt system reset, the microprocessor’s irq_h<3:0> pins are driven by the clockdivisor values set by four jumpers on J1. During n

3.8 Reset and Initialization3.8 Reset and InitializationA TL7702B power monitor senses +3 V dc to ensure that it is stable beforethe 21164 CPU’s input

3.8 Reset and InitializationFigure 3–6 System Reset and Initializationeb164.40Fan SensorPower SupplyReset SwitchJ30p_dcok+3 Vsense_disfan_ok_l2eb164.4

3.9 Serial ROM3.9 Serial ROMThe serial ROM (SROM) provides the following functions:• Initializes the CPU’s internal processor registers (IPRs)• Sets u

3.10 dc Power DistributionFigure 3–7 SROM and Serial Portsrom_datsrom_oe_lPLDsrom_clksrom_clk_ltest_srom_d_lJ13eb164.30eb164.2821164eb164.2SROMeb164.4

3.10 dc Power DistributionFigure 3–8 dc Power DistributionISA Conn. PCI32 Conn.Pull−Downs+5 V Pull−UpsIntegratedCircuits/ClocksSpkr+3 V Pull−UpsFan211

3.11 System Software3.11 System SoftwareEB164 software consists of the following:• Serial ROM code• Mini-Debugger code• Debug monitor ROM code• Window

3.11 System SoftwareFor additional information, refer to the Alpha Microprocessors SROM Mini-Debugger User’s Guide.3.11.3 Debug Monitor ROM CodeThe EB

C Technical Support and Ordering InformationC.1 Obtaining Technical Support ... C–1C.2 Ordering Digital Semiconductor Product

4System Address MappingThis chapter describes the mapping of the 40-bit processor physical addressspace into cacheable and noncacheable memory address

4.1 Physical Memory RegionsTable 4–1 Three Physical Memory RegionsRegion Address Range16DescriptionCacheable 00.0000.0000–7F.FFFF.FFFF Write-back cach

4.1 Physical Memory RegionsTable 4–2 Physical Memory Regions (Detailed)Region16Description00.0000.0000–00.3FFF.FFFF Cacheable memory space (1GB)00.400

4.1 Physical Memory RegionsCautionDue to CIA chip pin constraints, CPU address bits <38:35> are notbrought onchip. Software must ensure that CPU

4.2 21164 Address Mapping to PCI Space4.2.1 Cacheable Memory Space (00.0000.0000 Through 00.3FFF.FFFF)The EB164 recognizes the first 1GB of the physica

4.2 21164 Address Mapping to PCI Space• Software must use longword load or store instructions (LDL/STL) toperform a reference that is of longword leng

4.2 21164 Address Mapping to PCI SpaceTable 4–3 PCI Sparse Memory Space Byte-Enable GenerationLength1CPU Address<6:5>CPU Address<4:3>PCI B

4.2 21164 Address Mapping to PCI SpacePCI address bits <31:26> are obtained from either the hardware extensionregister (HAE_MEM), or the CPU add

4.2 21164 Address Mapping to PCI SpaceFigure 4–2 PCI Sparse Memory Space Address Translation—Region 2 CPU Address<4:3> Generated from INT4_VALID

B–1 Write Cycle Timing ... B–6B–2 Special Header Content . . ... B–9Tables1–1 Main Memory Sizes .

4.2 21164 Address Mapping to PCI Spaceto address a 32MB region that can be relocated by using the HAE_IO registerlocated in the CIA chip.4.2.4 PCI Spa

4.2 21164 Address Mapping to PCI SpaceTable 4–6 PCI Sparse I/O Space Byte-Enable GenerationLength1CPU Address<6:5>CPU Address<4:3>PCI Byte

4.2 21164 Address Mapping to PCI SpaceFigure 4–4 PCI Sparse I/O Space Address Translation—Region A CPU AddressLength in BytesByte OffsetPCI Address0

4.2 21164 Address Mapping to PCI Space4.2.5 PCI Dense Memory Space (86.0000.0000 Through 86.FFFF.FFFF)PCI dense memory space is typically used for PCI

4.2 21164 Address Mapping to PCI SpaceNoteIf the data written by the processor has holes, that is, some of thelongwords have been masked out, the corr

4.2 21164 Address Mapping to PCI SpaceThere are two classes of targets for PCI configuration read and writecommands: devices on the primary PCI bus and

4.2 21164 Address Mapping to PCI SpaceTable 4–7 PCI Configuration Space DefinitionBus Hierarchy PCI_AD Bits DefinitionLocal <31:24> Forced to 0 by

4.2 21164 Address Mapping to PCI SpaceTable 4–8 PCI Configuration Space Byte-Enable GenerationLength1CPU addr_h<6:5> CPU addr_h<4:3>PCI Byt

4.2 21164 Address Mapping to PCI SpaceTable 4–9 CPU Address Encoding for PCI Device SelectionCPU Address <20:16> PCI Address Bit IDSEL00000 pci_

4.2 21164 Address Mapping to PCI SpaceTable 4–10 EB164 Primary PCI IDSEL MappingIDSEL Device PCI Address Bit Physical AddressPCI slot 2 pci_ad<16&g

A–8 Flash ROM Memory Addresses (Within Segment) . . ... A–13A–9 Map of Flash ROM Memory . . ... A–13A–10 Flash ROM Configurati

4.2 21164 Address Mapping to PCI SpaceTable 4–11 Hardware-Specific Register SpaceCPU Address<39:28> Selected RegionCPU Address<27:6>CPU Add

4.2 21164 Address Mapping to PCI SpaceTable 4–12 PCI Target Window EnablesPCI_MASK<31:20>1Size of Window2Value ofn30000 0000 0000 1MB 200000 000

4.2 21164 Address Mapping to PCI SpaceNoteThe window base addresses should be on NATURALLY ALIGNEDaddress boundaries, depending on the size of the win

4.2 21164 Address Mapping to PCI SpaceTable 4–13 PCI Target Address Translation—Direct Mapped (SG MappingDisabled)PCI_MASK<31:20> Translated Add

4.2 21164 Address Mapping to PCI SpaceTable 4–14 Scatter-Gather Map AddressPCI_MASK<31:20>Size ofWindowScatter-GatherMap TableSize Scatter-Gathe

4.2 21164 Address Mapping to PCI SpaceFigure 4–7 PCI to System Bus Scatter-Gather Address Translation MapPeripheral Page Number Offset31MK−2306−11413

4.2 21164 Address Mapping to PCI SpaceAn 8-entry translation-lookaside buffer (TLB) is provided in the CIA chip forscatter-gather map entries. The TLB

4.2 21164 Address Mapping to PCI Space2. Bits <20:1> of the map entry (PTE) are used to generate the physicalpage address. This address is appen

5Power and Environmental RequirementsThis chapter describes the evaluation board power and environmentalrequirements, and physical board parameters.5.

About This GuideThis guide describes Digital Semiconductor’s 21164 Alpha MicroprocessorEvaluation Board (also called the EB164), an evaluation and dev

5.2 Environmental Requirements5.2 Environmental RequirementsThe 21164 microprocessor is cooled by a small fan blowing directly into thechip’s heat sin

5.3 Physical Board ParametersFigure 5–1 Board Component LayoutMK−2306−321111234567891011121314151617181920211(13.05 in)33.15 cm(12.10 in)30.73 cmPower

5.3 Physical Board ParametersTable 5–2 Board Component ListLocatorNumberComponentNumber Component Description1 U42 Digital Semiconductor 21164 Alpha m

AI/O Space Address MapsThis appendix provides lists of the physical EB164 I/O space assignments,including CIA operating register address space maps an

A.2 PCI Sparse I/O SpaceA.2.1 PCI Sparse I/O Space—Region APCI sparse I/O space—region A—occupies physical addresses 85.8000.0000through 85.BFFF.FFFF.

A.2 PCI Sparse I/O SpaceTable A–1 (Cont.) PC87312 Combination Controller Register Address SpaceMapAddress OffsetRead/WritePhysicalAddress RegisterIDE

A.2 PCI Sparse I/O SpaceTable A–1 (Cont.) PC87312 Combination Controller Register Address SpaceMapAddress OffsetRead/WritePhysicalAddress RegisterCOM2

A.2 PCI Sparse I/O SpaceTable A–1 (Cont.) PC87312 Combination Controller Register Address SpaceMapAddress OffsetRead/WritePhysicalAddress RegisterDisk

A.2 PCI Sparse I/O SpaceA.2.1.2 8242AH Keyboard and Mouse Controller AddressesTable A–2 lists the register and memory addresses for the keyboard/mouse

A.2 PCI Sparse I/O SpaceTable A–3 Time-of-Year Clock Device AddressesOffsetLatchedIndexPhysicalAddress Register70 0 85.8000.0E00 Seconds70 1 85.8000.0