Digital Equipment Corporation EK-SWRA2-IG Specifications

digital equipment corporationmaynard, massachusettsAlphaServer 8200/8400System Technical Manual Order Number EK–T8030–TM. A01The Digital AlphaServer

xDDR0:3—Data Diagnostic Registers ... 7-1067.6 I/O Port-Specific Registers...

4-6 Memory Subsystem• State transition due to TLSB activityTable 4-3 shows how the cache state can change due to bus activity.TLSB writes always cle

Memory Subsystem 4-7 Table 4-2 State Transition Due to Processor ActivityProcessorRequest Tag Probe Result1Action on TLSBTLSBResponseNext Ca

4-8 Memory Subsystem Table 4-3 State Transition Due to TLSB ActivityTable 4-4 shows how the CPU module responds to bus activity directed atthese ad

Memory Subsystem 4-9the write must be reissued by the DECchip 21164 to the TLSB as a WriteBlock. In the case that the Set Dirty bit is held o

4-10 Memory SubsystemDuring memory writes, TLSB memory modules store write data and ECCcheck bits as they are received off the TLSB. A minor modifi

Memory Subsystem 4-114.3.1.1 Control Address Interface The control address interface (CTL) is a single gate array. It provides theinterface

4-12 Memory SubsystemDRAM arrays. The MDI includes data buffers, ECC checking logic, self-test data generation and checking logic, and CSRs. MDI con

Memory Subsystem 4-13four memory modules, with at least two strings each, supports a maximumof 8-way interleaving.4.3.2 Memory Organization

4-14 Memory Subsystem Figure 4-5 Two-Way Interleave of a 128-Mbyte DRAM ArrayMemory modules of different capacities can be interleaved as a set with

Memory Subsystem 4-15module can result in reduced system throughput due to common data pathcontention between the two banks. At the module le

xi 4-3 Cache Index and Tag Mapping to Block Address (16MB)... 4-4 4-4 Memory Module Block Diagram ...

4-16 Memory Subsystemgroup of DRAM arrays. The default mode optimizes interleaving of mem-ory in any arrangement of memory modules. If the FEPROM

Memory Subsystem 4-17sole to locate and map out bad areas of physical address space. Self-test isinvoked during system power-up, when a TLS

4-18 Memory SubsystemTo exercise the array at its maximum operating speed, banks 0 and 1 arealways interleaved during self-test if the module conta

Memory Subsystem 4-19NOTE: Successful execution is not a measure of the array integrity. It indicates thatevery location in memory space has

4-20 Memory Subsystem Table 4-8 Self-Test Times: Moving Inversion, No Errors Found Module Capacity (Mbytes) Test Ti

Memory Interface 5-1Chapter 5Memory InterfaceThe memory interface to the TLSB consists of three parts:• Control address interface• Memory dat

5-2 Memory Interface5.1.1.1 Memory Bank State MachineThe CTL contains two TLSB control state machines, one for each memorybank. The state machines

Memory Interface 5-3command is one of the factors in determining if the command is acknowl-edged (TLSB_CMD_ACK) by this node. Table 5-1 show

5-4 Memory Interfacereceived from the TLSB bus. TLSB_SEND_DATA is also used to check forproper bus sequencing. Note that the TLSB_CMD_ACK and TLSB

Memory Interface 5-5• Write • Refresh The TLSB memory is designed to operate within the following TLSB clockcycle times: • 10.0 to 11.299 ns

xii 2-7 TLSB Node Base Addresses ... 2-28 2-8 TLSB CSR Address M

5-6 Memory Interface Table 5-2 Two Strings—128MB/512MB Row/Column Address Bit Swapping5.1.3.2 256MB/1024MB Memory Module AddressingTable 5-3 shows

Memory Interface 5-7 Table 5-3 Four Strings—256MB/1024MB Row/Column Address Bit Swapping5.1.3.3 512MB/2048MB Memory Module AddressingTable 5

5-8 Memory Interface Table 5-4 Eight Strings—512MB/2048MB Row/Column Address Bit SwappingDRAM TypeNo. of BanksInterleavedDRAM Address

Memory Interface 5-95.2 Memory Data InterfaceThe memory data interface (MDI) is comprised of four chips connected tothe DRAM array on one si

5-10 Memory Interface Figure 5-1 64-Bit ECC Coding SchemeThe received write data is checked for ECC errors. Any detected error islogged as appropri

Memory Interface 5-115.2.2.5 Write Data Out SelectionA 2:1 multipexer and a tristate enable capability are provided for interfac-ing the writ

5-12 Memory Interfaceon all CSR reads from memory. The ECC bits are generated across bits<63:0> and transmitted on TLSB_ECC<7:0>.5.2.4

Memory Interface 5-13in these bits. This field is undefined when either CRECC, CWECC, orECC is zero.5.3 CSR InterfaceThe CSR interface, use

5-14 Memory Interface• Multiplexing of local CTL CSRs and the data bytes within them • Byte-wide parity generation and checking of the CSRCA bus 5.3

Memory Interface 5-15The memory adapter supports TLSB broadcast writes to its MCR registerat address location BSB+1880 (byte address). This

xiii 6-30 DMA Masked Write Packet Sizes ... 6-58 6-31 DMA Unmasked Write

5-16 Memory Interfaceonto the CSRCA bus during a read of one of its internal CSRs. During awrite command to one of the CTL’s CSRs, a LD_EN signal f

Memory Interface 5-17 Table 5-7 CSRCA Data Bus MasterFor a read command, the selected chip drives the appropriate data on theCSRCA bus. Eac

5-18 Memory Interface5.3.2.4 CSRCA ParityThe CSRCA bus is protected by byte-wide odd parity. All data transmittedover this bus is accompanied by a

I/O Port 6-1Chapter 6I/O PortThe I/O port is the interface of the I/O subsystem to the TLSB bus. Twomodules can be used for I/O operations:

6-2 I/O PortThe I/O port interfaces the TLSB bus to up to four different I/O busesthrough separate I/O bus adapter modules. Digital provides three

I/O Port 6-3The two Up Hose HDRs receive packets from the four Up Hoses (two hoses per HDR) and transmit them to the IDRs through the Turbo V

6-4 I/O Portmation between the TLSB and I/O adapter modules by transmitting andreceiving packets across the hose(s). Mailbox, I/O window, device i

I/O Port 6-5 Table 6-1 I/O Port Transaction Types6.3.1 Mailbox TransactionsSome systems provide access to CSRs on external I/O buses (I/O

6-6 I/O PortThe I/O port can support up to 16 CPU chips. However, if more than fourCPU chips are present, any additional CPU chip must share a TLMB

I/O Port 6-76.3.2 I/O Window Space TransactionsCSRs that exist on some external I/O buses are accessed through I/O win-dow space transactio

xiv 7-50 STDER A, B, C, D Register Bit Definitions... 7-104 7-51 STDERE Register Bit Defin

6-8 I/O Port6.3.2.2 CSR Read Transactions to I/O Window SpaceA CSR read command to node 4 through 8 I/O window space causes an I/Oport installed in

I/O Port 6-9Therefore, when an interrupt occurs on an I/O bus (that is, XMI, Future-bus+, or PCI), the I/O bus adapter must first acquire the

6-10 I/O Port• I/O port generated error interrupts transmit a special vector on the TLSB, which must be preloaded by system software into the I/O po

I/O Port 6-11DMA IREAD command, the XMI I/O adapter acknowledges the IREADand pends the transaction. This frees the XMI for other bus traff

6-12 I/O Portrequires a single TLSB bus write transaction and is always a doublehexword. A DMA write request packet is executed as a disconnected (w

I/O Port 6-13detected on the Up Hose (for example, a parity error or sequence error), orif the TLSB bus Read-Modify-Write operation is unsuc

6-14 I/O PortWhen an I/O port receives a window write status return packet on the UpHose, it decrements its remote adapter node buffer counters and

I/O Port 6-15must not overwrite a mailbox that is still in use (<DONE> not set by theI/O port).The I/O system architecture requires t

6-16 I/O Port Figure 6-3 Sparse Address Space ReadsThe returned quadword data for a sparse window read command is repli-cated four times on the firs

I/O Port 6-17 Table 6-3 Sparse Address Space Read Field Descriptions6.4.2.2 Sparse Address Space WritesFigure 6-5 illustrates the TLSB addre

xvPrefaceIntended AudienceThis manual is intended for developers of system software and for servicepersonnel. It discusses the AlphaServer 8200/8400

6-18 I/O Port Figure 6-5 Sparse Address Space Writes Figure 6-6 Sparse Address Space Write DataBXB0797.AI0123456789101112131415161718192021222324252

I/O Port 6-19 Table 6-4 Sparse Address Space Write Field DescriptionsNote that the CSR data size on the TLSB is always a hexword. Valid bit

6-20 I/O Port Table 6-5 Sparse Address Write Length EncodingNOTE: The byte-length code is transmitted on the hose as LEN<1:0>. The Lengthf

I/O Port 6-21 Table 6-6 Dense Address Space Transaction Field DescriptionsThe data appears on the first data cycle of the TLSB data bus. Ei

6-22 I/O Port Figure 6-8 Dense Address Space Write DataThe returned hexword data for a dense window read command is asserted on the first data word

I/O Port 6-236.5 TLSB InterfaceAll TLSB bus transactions consist of one command/address cycle on the ad-dress bus and two data cycles on the

6-24 I/O Port Table 6-7 Transaction Types Supported by the I/O PortThe I/O port performs three primary functions on the TLSB: • DMA transactions

I/O Port 6-25 Table 6-8 Wrapped ReadsInterlocked Read/Unlock Write TransactionsVAX CI-port architecture (VAXport) devices require Interlocke

6-26 I/O PortModify-Write on the TLSB. The quadword of data that the I/O devicesends in the masked write command contains the original data with th

I/O Port 6-27and so on. Figure 6-10 shows the format of the data used by the I/O port inthe CSR write (interrupt) transaction. Figure 6-10

xviKFTIA and KFTHA support the PCI bus, XMI bus, and the Futurebus+,depending on the system in which they are used. The chapter describesthe transact

6-28 I/O Porthose). The I/O port, however, could post up to five interrupts to the CPUsat IPL 17 (one per hose plus one I/O port generated error i

I/O Port 6-29in strict first-come, first-served order. Any other writes to the TLMBPRregister by a CPU that already has two mailbox transact

6-30 I/O PortIf the Error bit is set in the window Read Data Return packet, the I/O portgenerates a TLSB CSR (broadcast) write to the CSR Read Data

I/O Port 6-316.5.2.1 Node 8 I/O Port Arbitration Mode SelectionSeveral mode-selectable lockout avoidance algorithms are implemented toguarant

6-32 I/O Port Figure 6-11 Minimum Latency ModeNote that NEXT_REQ_HI<n> would have become asserted in cycle 6 evenif the I/O port did not reque

I/O Port 6-33the Write Bank Unlock portion of a Read-Modify-Write operation. Figure6-13 shows the flow for this arbitration mode. Figure 6-1

6-34 I/O Portcommands are necessary to ensure an atomic operation and maintaincache coherency. 6.5.2.3 Bank Collision Effect on PriorityA bank coll

I/O Port 6-356.6 Hose InterfaceThe I/O port communicates with the I/O bus adapters over dual-cablebuses. These buses are called hoses. Th

6-36 I/O Portport receives a Window Status Return packet on the Up Hose, it decre-ments that hose’s counter. The I/O port does not transmit windowr

I/O Port 6-376.6.2.1 Sparse Address MappingA sparse address space uses low-order TLSB address bits to encode thesize of the access and its by

xvii Table 1 Digital AlphaServer 8200/8400 DocumentationTitle Order NumberHardware User Information and InstallationOperations ManualEK–T8030–OPSite P

6-38 I/O Port Table 6-10 Down Hose Signals Table 6-11 Up Hose SignalsTable 6-12 shows the UPCTL<3:0> L encoding.Signal DescriptionDND<31:

I/O Port 6-39 Table 6-12 UPCTL<3:0> EncodingTable 6-13 shows the information given by the hose status signals.6.6.4 Hose Packet Spec

6-40 I/O Port Table 6-13 Hose Status Signals Table 6-14 Down Hose Packet Type CodesSignals

I/O Port 6-41Mailbox Command PacketThe Mailbox Command packet is used by processors to access control and status registers in adapters on the

6-42 I/O Port Table 6-15 Mailbox Command Packet DescriptionDMA Read Data Return PacketThe DMA Read Data Return packet returns data previously reque

I/O Port 6-43The DMA Read Data Return packet is supported by the Mailbox Only, I/OWindow, Full, and Memory Channel variants of the hose proto

6-44 I/O PortDMA Read Data Return packet with the error bit set is returned across theDown Hose. Figure 6-16 DMA Read Data Return Packet with Error

I/O Port 6-45not return an INTR/IDENT Status Return packet. Figure 6-17 shows theINTR/IDENT Status Return packet. Figure 6-17 INTR/IDENT Sta

6-46 I/O Port Table 6-19 Sparse Window Read Command Packet DescriptionSparse Window Write Command PacketThe Sparse Window Write command packet is u

I/O Port 6-47 Figure 6-19 Sparse Window Write Command PacketTable 6-20 gives the description of the Sparse Window Write Commandpacket. Dense

xviiiTable 1 Digital AlphaServer 8200/8400 Documentation (Continued)Title Order NumberKZMSA Adapter Installation GuideEK–KXMSX–INRRDCD Installation G

6-48 I/O Port Table 6-20 Sparse Window Write Command Packet Description Figure 6-20 Dense Window Read Command PacketTable 6-21 gives the descriptio

I/O Port 6-49 Table 6-21 Dense Window Read Command Packet DescriptionField DescriptionClock 1, <31:30>Are always zero. Clock 1, <29

6-50 I/O Port Figure 6-21 Dense Window Write Command PacketTable 6-22 gives the description of the Dense Window Write Commandpacket. 31 30 29 26 25

I/O Port 6-51 Table 6-22 Dense Window Write Command Packet Description Figure 6-22 Byte Mask Field Memory Chanel Write PacketThe Memory Chan

6-52 I/O Port Figure 6-23 Memory Channel Write PacketTable 6-23 gives the description of the Memory Channel Write packet. 6.6.4.2 Up Hose Packet Sp

I/O Port 6-53 Table 6-23 Memory Channel Write Packet Description Figure 6-24 Mailbox Status Return PacketTable 6-24 gives the description of

6-54 I/O Port Table 6-24 Mailbox Status Return Packet DescriptionDMA ReadThe DMA Read packet is a request on the Up Hose from the I/O bus adapter t

I/O Port 6-55 Table 6-25 DMA Read Packet Description ADR<39:0> is the target address for the TLSB memory read. It must benaturally a

6-56 I/O Port Figure 6-26 Interlock Read PacketTable 6-27 gives the description of the IREAD packet. Table 6-27 Interlock Read Packet Description

I/O Port 6-57DMA Masked Write with DataThe DMA Masked Write Packet is a request on the Up Hose from the I/O bus adapter to the I/O port for a

xix Table 2 Related DocumentsTitle Order NumberGeneral Site PreparationSite Environmental Preparation GuideEK–CSEPG–MASystem I/O OptionsBA350 Modular

6-58 I/O Port Table 6-29 DMA Masked Write Packet DescriptionADR<39:0> is the target address for the DMA masked write and must be naturally al

I/O Port 6-59DMA Unmasked Write with DataThe DMA Unmasked Write packet is a request on the Up Hose from theI/O bus adapter to the I/O port f

6-60 I/O Port Table 6-31 DMA Unmasked Write Packet DescriptionADR<39:0> is the target address for the memory write and must be natu-rally ali

I/O Port 6-61 Table 6-32 INTR/IDENT Status Return Packet DescriptionSparse Window Read Data Return PacketThe Sparse Window Read Data return

6-62 I/O Port Table 6-33 Sparse Window Read Data Return Packet DescriptionDense Window Read Data Return PacketThe Dense Window Read Data Return pac

I/O Port 6-63 Figure 6-31 Dense Window Read Data Return PacketTable 6-34 gives the description of the dense window read data returnpacket.

6-64 I/O PortWindow Write Status Return PacketThe Window Write Status Return packet is used by adapters on remote buses that support I/O window spac

I/O Port 6-656.6.5 Hose ErrorsFour types of errors affect the hoses: • Parity errors on the transmitted data/control information• Illegal p

6-66 I/O Port6.7 I/O Port Error HandlingThe I/O port provides a high reliability electrical environment. Conse-quently, error handling is biased t

I/O Port 6-67If the I/O port detects a hard internal error. it sets the appropriate errorbit in either the ICCNSE register or one of the IDP

First Printing, May 1995The information in this document is subject to change without notice and should not be construed as a com-mitment by Digital E

6-68 I/O PortEach IDR on the I/O port receives 64 data bits and 8 ECC bits from the TLSB. Error checking is performed and if a data error is detect

I/O Port 6-69another node and ensure that TLSB_FAULT is only asserted for two cy-cles.When the I/O port detects assertion of TLSB_FAULT on th

6-70 I/O PortHose PWROK Transitioned and Hose Error are technically hose errors, not internal I/O port errors. However, they are handled by the I/O

I/O Port 6-71The I/O port assertion checks TLSB_CMD_ACK only when it is being as-serted by the the I/O port. If the I/O port detects a misma

6-72 I/O Porttected, the I/O port does not issue the transaction on the TLSB. It simplyaborts that transaction by transmitting a UTV_ERROR_A (or B)

I/O Port 6-73ting <UECC>. A UECC error causes the I/O port to set TLBER<UDE>and assert TLSB_DATA_ERROR. An IPL 17 is also poste

6-74 I/O Port6.7.8.6 Transmit Check ErrorsThe I/O port level checks the TLSB_D<255:0> and TLSB_ECC<31:0>fields when it is driving data o

I/O Port 6-75• The TLFADRn registers record the address, command, and bank num-ber from the command.These registers can only hold information

6-76 I/O PortThe ICR up Turbo Vortex interface checks for the following types of errors:• Parity errors• Sequence errors• Buffer overflow errors• I

I/O Port 6-77assertion of this signal causes ICCNSE<DN_VRTX_ERRORn> to set. AnIPL 17 interrupt will also be posted if ICCNSE<INTR_N

Overview 1-1Chapter 1OverviewThe computer system is an AlphaGeneration server very similar to butwith twice the performance of DEC 7000/10000

6-78 I/O Portserts TLSB_FAULT. The catastrophic failure requires a reset of the I/Oport to return the I/O port to a known state. 6.7.11.4 Hose Stat

I/O Port 6-79• One external hose connection• Optional multimode FDDI daughter card or UTP FDDI daughter card• Optional 4-Mbyte NVRAM daughter

6-80 I/O Portsupports one Turbo Vortex bus (Turbo Vortex Bus A) and two hose buses:internal hose (Hose 0) and external hose (Hose 1).The integrated

I/O Port 6-81 Figure 6-35 Integrated I/O Section of the KFTIA6.8.1.1 PCI InterfaceThe PCI interface provides a host bridge to two physical PC

6-82 I/O PortThe PCI interface consists of the following sections: • Two HPC (hose to PCI) gate arrays • Map RAM• Up Hose control logic These sectio

I/O Port 6-836.8.1.3 Ethernet PortsThe integrated I/O port supports two Ethernet ports and uses the twisted-pair (10baseT) connection. The

6-84 I/O Port6.8.2.2 Mailbox TransactionAll mailbox transactions are executed by the HPC as a PCI master.Mailbox transactions forwarded from the HDR

I/O Port 6-85rupt’s vector and merging it with a programmable device IPL. TheINTR/IDENT is then sent to the HDR over the Up Hose. Because th

System Registers 7-1Chapter 7System RegistersThe system registers are divided into two main groups:• TLSB registers• Node-specific registersT

1-2 OverviewFuturebus+, or PCI bus. The local I/O options on the integrated I/Oport appear to software as a PCI bus connected to a hose.Figure 1-1

7-2 System Registers• When the value of a bit position is given explicitly in a register dia-gram, the information conveyed is as follows:• The entr

System Registers 7-3 Table 7-1 TLSB Node Space Base Addresses Node Module Physical Base Address (BB) Address Field &

7-4 System Registers7.3 TLSB RegistersTable 7-2 lists the TLSB registers. Descriptions of registers follow. Table 7-2 TLSB RegistersMnemonic Name

System Registers 7-5TLDEV—Device Register Table 7-3 TLDEV Register Bit DefinitionsAddressAccessBB + 0000 R/WThe TLDEV register is loaded du

7-6 System Registers Table 7-3 TLDEV Register Bit Definitions (Continued)Name Bit(s) Type FunctionDTYPE<15:0> R/W, 0 Device Type. Identifi

System Registers 7-7TLBER—Bus Error RegisterAddressAccessBB + 0040 R/WThe TLBER register contains bits that are set when a TLSB nodedetects e

7-8 System Registers Table 7-4 TLBER Register Bit DefinitionsName Bit(s) Type FunctionDTO<31> W1C, 0 Data Timeout. Set when a commanding no

System Registers 7-9Table 7-4 TLBER Register Bit Definitions (Continued)Name Bit(s) Type FunctionDS3<23> R, U Data Syndrome 3. A stat

7-10 System RegistersTable 7-4 TLBER Register Bit Definitions (Continued)Name Bit(s) Type FunctionUDE<16> W1C, 0 Uncorrectable Data Error. S

System Registers 7-11Table 7-4 TLBER Register Bit Definitions (Continued)Name Bit(s) Type FunctionACKTCE<6> W1C, 0 Acknowledge Transmi

Overview 1-3bus transactions may be overlapped, and these transactions may be over-lapped with bus arbitration. Arbitration priority rotates

7-12 System RegistersTable 7-4 TLBER Register Bit Definitions (Continued)Name Bit(s) Type FunctionBAE<2> W1C, 0 Bank Available Violation Erro

System Registers 7-13Table 7-4 TLBER Register Bit Definitions (Continued)Name Bit(s) Type FunctionATCE<0> W1C, 0 Address Transmit Chec

7-14 System RegistersTLCNR—Configuration RegisterAddressAccessBB + 0080R/WThe TLCNR register contains the TLSB system configuration setupand status

System Registers 7-15 Table 7-5 TLCNR Register Bit DefinitionsName Bit(s) Type FunctionLOFE<31> R/W, 0 Lock on First Error. If set, t

7-16 System RegistersTable 7-5 TLCNR Register Bit Definitions (Continued)Name Bit(s) Type FunctionSTF_B<13> R/W, 1 Self-Test Fail B. When se

System Registers 7-17Table 7-5 TLCNR Register Bit Definitions (Continued)Name Bit(s) Type FunctionVCNT<11:8> R/W, 0 Virtual Unit Count

7-18 System RegistersTable 7-5 TLCNR Register Bit Definitions (Continued)Each node on the TLSB can contain up to two individually addressableunits.

System Registers 7-19TLVID—Virtual ID Register AddressAccessBB + 00C0R/WThe TLVID register contains the TLSB virtual identifiers assignedto a

7-20 System Registers Table 7-6 TLVID Register Bit DefinitionsName Bit(s) Type FunctionRSVD<31:8> R/W, 0 Reserved. Must be written as zero.V

System Registers 7-21TLMMRn—Memory Mapping Registers Table 7-7 TLMMRn Register Bit DefinitionsAddressAccessBB + 0200 to BB + 03C0W (CPU), R

1-4 Overviewto the DECchip 21164 Functional Specification for a complete descriptionof the DECchip 21164 and PALcode. 1.3.2 Backup CacheEach backu

7-22 System RegistersTable 7-7 TLMMRn Register Bit Definitions (Continued) Table 7-8 Interleave Field Values for Two-Bank Memory ModulesName Bit(

System Registers 7-23 Table 7-9 Address Ranges Selected by ADRMASK Field Values<ADRMASK>AddressRangeTLSB_ADR BitsComparedTLSB_ADR Bits

7-24 System RegistersTLFADRn—Failing Address Registers Table 7-10 TLFADRn Register Bit DefinitionsAddressAccessBB + 0600, 0640R/WThe TLFADRn regis

System Registers 7-25Table 7-10 TLFADRn Register Bit Definitions (Continued)The TLFADRn registers are updated on the following conditions, l

7-26 System RegistersTLESRn—Error Syndrome Registers Table 7-11 TLESRn Register Bit DefinitionsAddressAccessBB + 0680 through 0740R/WThe TLESRn re

System Registers 7-27Table 7-11 TLESRn Register Bit Definitions (Continued)Name Bit(s) Type FunctionCPU1RSVDRSVD<23> RO, 0R0R0CPU 1.

7-28 System RegistersTable 7-11 TLESRn Register Bit Definitions (Continued)The four TLESRn registers are independent of each other. Each registerd

System Registers 7-29Four error bits in the TLBER register will set as a result of the five errorbits in this register.• CRECC sets TLBER<

7-30 System RegistersTLILIDn—Interrupt Level IDENT Registers Table 7-12 TLILIDn Register Bit DefinitionsNOTE: An internally generated I/O port er

System Registers 7-31TLCPUMASK—CPU Interrupt Mask Register Table 7-13 TLCPUMASK Register Bit DefinitionsAddressAccessBB + 0B00R/WThe TLCPUM

Overview 1-5ported by a single motherboard design. The 2-Gbyte memory option uses a different motherboard and SIMM design. A maximum of seve

7-32 System RegistersTLMBPR—Mailbox Pointer Registers Table 7-14 TLMBPR Register Bit DefinitionsFigure 7-1 shows the mailbox data structure.Address

System Registers 7-33 Figure 7-1 Mailbox Data StructureTable 7-15 gives the description of the mailbox data structure fields. Table 7-15 Mai

7-34 System RegistersTable 7-15 Mailbox Data Structure Description (Continued)QW Bit(s) Name Description4<63:0> RDATA Read Data. For read c

System Registers 7-35TLIPINTR—Interprocessor Interrupt Register Table 7-16 TLIPINTR Register Bit DefinitionsTo post an interprocessor interr

7-36 System RegistersTLIOINTRn—I/O Interrupt Registers Table 7-17 TLI/OINTR Register Bit DefinitionsTo post an interrupt, the I/O port writes the

System Registers 7-37means that all CPUs accept writes to these registers. Multiple writes to aregister post multiple interrupts. Reads to

7-38 System RegistersTLWSDQR4-8—Window Space Decr Queue CounterRegistersAddressAccessBSB + 0400 through 0500R/WThe TLWSDQRn registers are used by an

System Registers 7-39TLRMDQRX—Memory Channel Decr Queue CounterRegister X AddressAccessBSB + 0600 R/WThe TLRMDQR register X is used by an I/O

7-40 System RegistersTLRMDQR8—Memory Channel Decr Queue CounterRegister 8 AddressAccessBSB + 0640 R/WThe TLRMDQR register 8 is used by an I/O node t

System Registers 7-41TLRDRD—CSR Read Data Return Data Register Table 7-18 TLRDRD Register Bit DefinitionsAddressAccessBSB + 0800 WThe TLRDRD

1-6 Overviewtion to two 10BaseT Ethernet ports, one FDDI port, and three FWD andone single-ended SCSI ports. The DWLMA is the interface between a h

7-42 System RegistersTLRDRE—CSR Read Data Return Error Register AddressAccessBSB + 0840 WThe TLRDRE register is used by I/O nodes to signal an error

System Registers 7-43TLMCR—Memory Control Register Table 7-19 TLMCR Register Bit DefinitionsAddressAccessBSB + 1880 WThe TLMCR register is u

7-44 System Registers7.4 CPU Module RegistersCPU module registers are divided into four groups:• Module-specific registers• CPU0-specific registers

System Registers 7-45 Table 7-20 CPU Module RegistersMnemonic Name AddressModule RegistersTLDIAGTLDTAGDATATLDTAGSTATTLMODCONFIGTLCON00TLCON0

7-46 System RegistersTable 7-20 CPU Module Registers (Continued) Table 7-21 Gbus RegistersMnemonic Name AddressModule RegistersRM_RANGE_0ARM_RANG

System Registers 7-47TLDIAG—Diagnostic Setup Register Table 7-22 TLDIAG Register Bit DefinitionsAddressAccessBB + 1000 R/WThe TLDIAG regist

7-48 System RegistersTable 7-22 TLDIAG Register Bit Definitions (Continued)Name Bit(s) Type FunctionASRT_FLTRSVDFDE<3:0>FDBERSVDDTCPDTRDDTWR

System Registers 7-49Table 7-22 TLDIAG Register Bit Definitions (Continued)Name Bit(s) Type FunctionDTWR<1> W, 0 DTag Write. When se

7-50 System RegistersTLDTAGDATA—DTag Data Register Table 7-23 TLDTAGDATA Register Bit DefinitionsAddressAccessBB + 1040R/WDiagnostics test the DTag

System Registers 7-51TLDTAGSTAT—DTag Status Register Table 7-24 TLDTAGSTAT Register Bit DefinitionsAddressAccessBB + 1080R/WDiagnostics test

Overview 1-7• KDM70 – XMI to SI disk/tape • KZMSA – XMI to SCSI disk/tape • KFMSB – XMI to DSSI disk/tape and OpenVMS clusters • CIXCD-AC – X

7-52 System RegistersTLMODCONFIG—CPU Module Configuration Register Table 7-25 TLMODCONFIG Register Bit DefinitionsAddressAccessBB + 10C0R/WThe TLM

System Registers 7-53Table 7-25 TLMODCONFIG Register Bit Definitions (Continued)NOTE: A write to the TLMODCONFIG register must be followed

7-54 System RegistersTLEPAERR— ADG Error Register AddressAccessBB + 1500R/WThe ADG Error Register contains CPU module error bits. Thesebits are set

System Registers 7-55 Table 7-26 TLEPAERR Register Bit DefinitionsName Bit(s) Type FunctionRSVDNO_ACKCSR_WR_NXMWSPC_RD_PENDIBOXTOWSPC_RD_ERR

7-56 System RegistersTable 7-26 TLEPAERR Register Bit Definitions (Continued)Name Bit(s) Type FunctionM2AAPE1M2AAPE0E2MAPE1E2MAPE0<3><2&g

System Registers 7-57TLEPDERR—DIGA Error Register AddressAccessBB + 1540R/WThe TLEPDERR register contains CPU module error bits. Thesebits ar

7-58 System Registers Table 7-27 TLEPDERR Register Bit DefinitionsName Bit(s) Type FunctionRSVDGBTO<31:3><2>R/W, 0W1C, 0Reserved. Must

System Registers 7-59TLEPMERR—MMG Error Register AddressAccessBB + 1580R/WThe TLEPMERR register contains CPU module error bits. Thesebits are

7-60 System Registers Table 7-28 TLEPMERR Register Bit DefinitionsName Bit(s) Type FunctionRSVDRSTSTATD2DCPE3D2DCPE2D2DCPE1<31:7><6><

System Registers 7-61Table 7-28 TLEPMERR Register Bit Definitions (Continued)Name Bit(s) Type FunctionD2MCPEA2MAPE1A2MAPE0<2><1>

1-8 Overview— Cache/memory exerciser— I/O port/DWLMA loopback exerciser — Disk/tape device exerciser — Network exerciser — FBE exerciser — XCT (XMI

7-62 System RegistersTLEP_VMG—Voltage Margining Register Table 7-29 TLEP_VMG Register Bit DefinitionsAddressAccessBB + 15C0R/WThe TLEP_VMG register

System Registers 7-63TLINTRMASK0–1—Interrupt Mask Registers AddressAccessBB + 1100, BB + 1140R/WThe TLINTRMASK0–1 registers are used to enab

7-64 System Registers Table 7-30 TLEPDERR Register Bit DefinitionsName Bit(s) Type FunctionRSVDCtrl/P_HALT_ENAHALT_ENAINTIM_ENAIP_ENAIPL17_ENAIPL16

System Registers 7-65TLINTRSUM0–1—Interrupt Source Registers AddressAccessBB + 1180, BB + 11C0R/WThe DECchip 21164 has seven interrupt lines.

7-66 System Registers Table 7-31 TLINTRSUM Register Bit DefinitionsName Bit(s) Type FunctionRSVDHALTCtrl/P_HALTIPL17_INTRIPL16_INTRIPL15_INTR<31

System Registers 7-67Table 7-31 TLINTRSUM Register Bit Definitions (Continued)Name Bit(s) Type FunctionIPL14_INTRINTIM_INTRIP_INTRIPL17_INT

7-68 System RegistersTLCON00,01,10,11—Console Communications RegsAddressAccessBB + 1200 & 1400; BB + 1300 & 1440R/WTwo 32-bit wide register

System Registers 7-69TLCON0A,0B,0C,1A,1B,1C—DIGA Comm. Test RegsThe Console Communications registers are implemented in DIGA0. Thesame regis

7-70 System RegistersRM_RANGE_nA,B—Memory Channel Range RegsAddressAccessBB + 1E00 through 1EC0R/WThe Memory Channel Range registers define the two

System Registers 7-71 Table 7-32 Memory Channel Range Register Bit DefinitionsName Bit(s) Type FunctionVALIDRSVDBASE_ADR<38:20> RSVDIN

TLSB Bus 2-1Chapter 2TLSB BusThis chapter provides a brief overview of the TLSB bus. For more detaileddiscussions and timing diagrams for th

7-72 System RegistersTLDMCMD—Data Mover Command RegisterAddressAccessBB + 1600R/WThe TLDMCMD register controls the data mover transactions.31 30 29

System Registers 7-73 Table 7-33 TLDMCMD Register Bit DefinitionsName Bit(s) Type FunctionDM_DONEIN_PROGRSVDCPU_IDRSVDRM_INTLVRM_4RM_3DM_CMD

7-74 System RegistersTable 7-33 TLDMCMD Register Bit Definitions (Continued)Name Bit(s) Type FunctionDM_CMDRSVDDM_8KBDM_4KBDM_2KBDM_1KBDM_512B<

System Registers 7-75TLDMADRA—Data Mover Source Address Register Table 7-34 TLDMADRA Register Bit DefinitionsAddressAccessBB + 1680WThe TLM

7-76 System RegistersTLDMADRB—Data Mover Destination Address Reg Table 7-35 TLDMADRB Register Bit DefinitionsAddressAccessBB + 16C0WThe TLMADRB re

System Registers 7-77GBUS$WHAMI Table 7-36 GBUS$WHAMI Register Bit DefinitionsAddressAccessFF C000 0000R/WThe GBUS$WHAMI register provides n

7-78 System RegistersGBUS$LED0,1,2AddressAccessFF C100 0000, FF C200 0000, FF C300 0000R/WThe GBUS$LEDn registers are used by diagnostics to indicat

System Registers 7-79GBUS$MISCRAddressAccessFF C400 0000RThe GBUS$MISCR register is used to gather various read bits thatshow module configur

7-80 System Registers Table 7-37 GBUS$MISCR Register Bit DefinitionsName Bit(s) Type FunctionCONWIN1RCONWIN0RRSVDTLSB_RUNTLSB_SECUREPROCNTCACSIZ<

System Registers 7-81GBUS$MISCW Table 7-38 GBUS$MISCW Register Bit DefinitionsAddressAccessFF C500 0000WThe GBUS$MISCW register is used to g

iiiContentsPreface ...

2-2 TLSB Bus2.1.1 TransactionsA transaction couples a commander node that issues the request and aslave node that sequences the data bus to transf

7-82 System RegistersGBUS$TLSBRSTAddressAccessFF C600 0000R/WThe GBUS$TLSBRST register is used to initiate a system reset se-quence. When this regi

System Registers 7-83GBUS$SERNUM Table 7-39 GBUS$SERNUM Register Bit DefinitionsAddressAccessFF C700 0000R/WThe GBUS$SERNUM register is used

7-84 System RegistersTable 7-39 GBUS$SERNUM Register Bit Definitions (Continued)Name Bit(s) Type FunctionEXPSELXMT_DATARCV_DATASROM_CLK<4:3>

System Registers 7-857.5 Memory-Specific RegistersTable 7-40 lists the memory-specific registers. Descriptions follow.Refer to Table 7-2 fo

7-86 System RegistersSECR—Serial EEPROM Control/Data Register Table 7-41 SECR Register Bit DefinitionsAddressAccessBB + 0000 1800 R/WThe SECR regi

System Registers 7-87MIR—Memory Interleave Register AddressAccessBB + 0000 1840R/WThe MIR register is used by memory to determine DRAM RAS se

7-88 System Registers Table 7-42 MIR Register Bit DefinitionsName Bit(s) Type FunctionVALID<31> R/W, 0 Valid. When set, enables the module

System Registers 7-89MCR—Memory Configuration RegisterAddressAccessBB + 0000 1880; BSB + 0000 1880R/WThe MCR register provides information ab

7-90 System Registers Table 7-43 MCR Register Bit DefinitionsName Bit(s) Type FunctionBAT<31> R, none1Battery OK. Indicates the state of the

System Registers 7-91Table 7-43 MCR Register Bit Definitions (Continued)Name Bit(s) Type FunctionOPTION<9> R, X1Option Installed. Th

TLSB Bus 2-3The TLSB implements parity checking on all address and command fieldson the address bus, ECC protection on the data field, and pr

7-92 System RegistersTable 7-43 MCR Register Bit Definitions (Continued)Name Bit(s) Type FunctionDTR<5:4> R/W, 0 DRAM Timing Rate. This fie

System Registers 7-93STAIR—Self-Test Address Isolation Register Table 7-44 STAIR Register Bit DefinitionsAddress segments are mapped accord

7-94 System Registers Table 7-45 STAIR Register Bit Correspondence of Memory Address SegmentsEach module executes self-test as if it were the only

System Registers 7-95STER—Self-Test Error RegisterAddressAccessBB + 0000 1900R/WThe STER register contains address information pertaining to

7-96 System Registers Table 7-46 STER Register Bit DefinitionsName Bit(s) Type FunctionRSVD<31:8> R0 Reserved. Read as zero.STE3<7> W1

System Registers 7-97MER—Memory Error Register Table 7-47 MER Register Bit DefinitionsAddressAccessBB + 0000 1940R/WThe MER register provide

7-98 System RegistersMDRA—Memory Diagnostic Register A Table 7-48 MDRA Register Bit DefinitionsAddressAccessBB + 0000 1980R/WMDRA register A is u

System Registers 7-99Table 7-48 MDRA Register Bit Definitions (Continued)Name Bit(s) Type FunctionRFR<29:28> R/W, 01 Refresh Rate. D

7-100 System RegistersTable 7-48 MDRA Register Bit Definitions (Continued)Name Bit(s) Type FunctionPOEM1<6> R/W, 01 Pause on Error Mode. Wh

System Registers 7-101Table 7-48 MDRA Register Bit Definitions (Continued)Name Bit(s) Type FunctionFCAPE<2> R/W, 0 Force Column Addre

2-4 TLSB BusTable 2-1 TLSB Bus Signals (Continued)Signal Name Default State FunctionTLSB_PS_TX LTLSB_EXP_SEL<1:0> LTLSB_SECURE LLDC_PWR_OK L

7-102 System RegistersMDRB—Memory Diagnostic Register B Table 7-49 MDRB Register Bit DefinitionsAddressAccessBB + 0000 19C0R/WMemory Diagnostic Reg

System Registers 7-103STDERA,B,C,D,E—Self-Test Data Error Registers The function of STDERA is slightly different from the other four register

7-104 System Registers Table 7-50 STDER A, B, C, D Register Bit DefinitionsTable 7-51 describes each field of self-test data error register E. Thi

System Registers 7-105 Table 7-51 STDERE Register Bit DefinitionsName Bit(s) Type FunctionRSVD<31:19> R0 Reserved. Read as zero.VRC&l

7-106 System RegistersDDR0:3—Data Diagnostic Registers Table 7-52 DDRn Register Bit DefinitionsAddressAccessBB + 0001 0140; 0001 04140; 0001 8140;

System Registers 7-107Table 7-52 DDRn Register Bit Definitions (Continued)Name Bit(s) Type FunctionEFLPD<15> R/W, 0 Enable Flip Data

7-108 System RegistersTable 7-52 DDRn Register Bit Definitions (Continued)Name Bit(s) Type FunctionICFR<2> R/W, 0 Inhibit Clear on Free Run.

System Registers 7-1097.6 I/O Port-Specific RegistersThe I/O port responds to all addresses within its node space. If, however,the I/O port

7-110 System RegistersRMRR0-1—Memory Channel Range RegistersAddressAccessBB + 1E00 to 1EC0 R/WThe I/O port houses two incoming Memory Channel addres

System Registers 7-111 Table 7-54 RMRR0-1 Register Bit DefinitionsName Bit(s) Type FunctionVALIDRSVDBASE_ADR<38:20> RSVDINTLV_ENEXT_MA

TLSB Bus 2-52.2 OperationThis section offers an overview of the TLSB bus operations. Topics in-clude: • Physical node identification• Virtu

7-112 System RegistersICCMSR—I/O Control Chip Mode Select Register Table 7-55 ICCMSR Register Bit DefinitionsAddressAccessBB + 2000 R/WThe ICCMSR r

System Registers 7-113Table 7-55 ICCMSR Register Bit Definitions (Continued)Name Bit(s) Type FunctionSUP_CTL<1:0><3:2> R/W, 0 S

7-114 System RegistersTable 7-55 ICCMSR Register Bit Definitions (Continued)Name Bit(s) Type FunctionSUP_CTL<1:0>ARB_CTL<1:0><3:2&g

System Registers 7-115Table 7-55 ICCMSR Register Bit Definitions (Continued)Name Bit(s) Type FunctionARB_CTL<1:0><1:0> R/W, 0AR

7-116 System RegistersTable 7-55 ICCMSR Register Bit Definitions (Continued)Name Bit(s) Type FunctionARB_CTL<1:0><1:0> R/W, 0ARB_CTL F

System Registers 7-117ICCNSE—I/O Control Chip Node-Specific Error RegAddressAccessBB + 2040R/WThe ICCNSE register logs the collective error i

7-118 System Registers Table 7-56 ICCNSE Register Bit DefinitionsName Bit(s) Type FunctionINTR_NSES<31> R/W, 0 Interrupt on NSES. When set,

System Registers 7-119Table 7-56 ICCNSE Register Bit Definitions (Continued)Name Bit(s) Type FunctionUP_VRTX_ERR<26:25> W1C, 0 Up Vor

7-120 System RegistersTable 7-56 ICCNSE Register Bit Definitions (Continued)Name Bit(s) Type FunctionMULT_INTR_ERR<22> W1C, 0 Multiple Inter

System Registers 7-121Table 7-56 ICCNSE Register Bit Definitions (Continued)Name Bit(s) Type FunctionUP_HOSE_PKT_ERR<15:12> W1C, 0 Up

2-6 TLSB Bus2.2.2 Virtual Node IdentificationTLSB system operation requires that certain functional units can be iden-tified uniquely, independent

7-122 System RegistersICCDR—I/O Control Chip Diagnostic RegisterAddressAccessBB + 2080R/WThe ICCDR register can be programmed by diagnostics to forc

System Registers 7-123 Table 7-57 ICCDR Register Bit DefinitionsName Bit(s) Type FunctionENA_DMA_HID<31> R/W, 0 Enable DMA Hose ID. W

7-124 System RegistersTable 7-57 ICCDR Register Bit Definitions (Continued)Name Bit(s) Type FunctionDIS_TLSB_FAULT<4> R/W, 0 Disable TLSB Fa

System Registers 7-125ICCMTR—I/O Control Chip Mailbox Transaction RegAddressAccessBB + 20C0RThe ICCMTR register indicates if a mailbox transa

7-126 System Registers Table 7-58 ICCMTR Register Bit DefinitionsName Bit(s) Type FunctionRSVD <31:4> R0 Reserved. Read as zeros. MBX_TIP<

System Registers 7-127ICCWTR—I/O Control Chip Window Transaction Reg Table 7-59 ICCWTR Register Bit DefinitionsAddressAccessBB + 2100RThe IC

7-128 System RegistersIDPNSE0–3—I/O Data Path Node-Specific Error Regs AddressAccessBB + 2A40, 2140, 2240, 2340R/WThe IDPNSE0–3 registers are physic

System Registers 7-129 Table 7-60 IDPNSE0–3 Register Bit DefinitionsName Bit(s) Type FunctionHOSEn_RESET<31> W, 0 HOSEn Reset. When t

7-130 System RegistersTable 7-60 IDPNSE0–3 Register Bit Definitions (Continued)Name Bit(s) Type FunctionIDR_UP_VRTX_ERR<26:25> W1C, 0 IDR Up

System Registers 7-131Table 7-60 IDPNSE0–3 Register Bit Definitions (Continued)Name Bit(s) Type FunctionHOSEn_PWROK_TR<3> W1C, X HOSE

TLSB Bus 2-7drive the address and command, the outcome of the tag lookup can beevaluated by the bus interface. If the lookup is a hit, then

7-132 System RegistersTable 7-60 IDPNSE0–3 Register Bit Definitions (Continued)Name Bit(s) Type FunctionHOSEn_PWROK<1> R, X HOSEn Power OK.

System Registers 7-133IDPDRn—I/O Data Path Diagnostic RegistersAddressAccessBB + 2A80, 2180, 2280, 2380R/WThe IDPDRn registers can be program

7-134 System Registers Table 7-61 IDPDR0–3 Register Bit DefinitionsName Bit(s) Type FunctionVOLT_MARG<31> R/W, 0 Voltage Margin. When set, t

System Registers 7-135Table 7-61 IDPDR0–3 Register Bit Definitions (Continued)Name Bit(s) Type FunctionFRC_VAL_SEQ_ERR<19> R/W, 0 For

7-136 System Registers Table 7-62 Error Matrix for Force Error BitsSet Diagnostic Bit Perform Transaction Detect ErrorIDPDR0<FRC_CSR_BUS_DPE>

System Registers 7-137IDPVR—I/O Data Path Vector Register Table 7-63 IDPVR Register Bit DefinitionsAddressAccessBB + 2B40R/WThe IDPVR regis

7-138 System RegistersIDPMSR—I/O Data Path Mode Select RegisterAddressAccessBB + 2B80R/WThe IDPMSR register can be used by software to select the de

System Registers 7-139 Table 7-64 IDPMSR Register Bit DefinitionsName Bit(s) Type FunctionRSVD<31:2> R/W, 0 Reserved. Read as zeros.

7-140 System RegistersIBR—Information Base Repair RegisterAddressAccessBB + 2BC0R/WThe IBR register is used to access the EEPROM located on the I/O

System Registers 7-141 Table 7-65 IBR Register Bit DefinitionsName Bit(s) Type FunctionRSVD<31:3> R/W, 0 Reserved. Read as zeros. SC

2-8 TLSB Bus2.2.3.1 Memory Bank Addressing SchemeThe TLSB supports one terabyte of physical memory. The memory ad-dress space is accessed by a 40-b

7-142 System Registers7.7 KFTIA Specific RegistersRegisters specific to the integrated I/O module, the KFTIA (registers in ad-dition to those speci

Interrupts 8-1Chapter 8InterruptsThe TLSB supports both vectored and nonvectored interrupts. • Vectored interrupts are the traditional I/O

8-2 Interrupts• At most, four interrupts at levels 0, 1, and 2 can be pending on theTLSB bus (one per interrupt level 14, 15, and 16, respectively,

Interrupts 8-3• The targeted CPUs are interrupted at an appropriate level and theCPU issues a CSR read transaction over the TLSB bus to the

8-4 InterruptsRefer to Chapter 7 for the format of all registers used in the interrupt op-eration.8.3.1.1 Virtual Node Identification - TLVIDTLSB sy

Interrupts 8-5only to TLIOINTR4. Interrupts at the IPL level(s) specified in bits<19:16> are targeted at the VIDs specified in bits &l

8-6 InterruptsTLIPINTR register and interrupts either (or both) of the CPUs as appro-priate, based on their virtual node IDs. The interprocessor in

Glossary-1GlossaryADGAddress gate array.BankSmallest group of DRAMs that can be interleaved. A bank consists of oneor more strings. Block64 byt

Glossary-2FNSFast, narrow, single-ended. FWDFast, wide, differential. Internal HoseThe connection (etch pathway) between the TLSB interface and the i

Glossary-3StringThe smallest group of DRAMs (144 1/4M x 4) needed to store and retrieve64 bytes of data per TLSB transaction. In some array impleme

TLSB Bus 2-92.2.3.3 Memory Bank Address DecodingThe minimum bank size for the TLSB address decode scheme is 64Mbytes. To address memory, a CP

Index-1IndexAABTCE, 7-8Accessing remote I/O CSRs, 6-15Accessing through I/O window space, 6-15Accessing through mailboxes, 6-14Access, remote I/O CSR,

Index-2A2MAPE1, 7-61BBackup cache, 1-4, 4-2BAE, 7-12BANKV, 7-24Bank address decoding, 2-9Bank available flags, 5-4Bank available status, 2-11Bank avai

Index-3Correctable Read Data Error bit, 7-9Correctable Read Data Error Interrupt Disablebit, 7-18Correctable Read ECC Error bit, 7-27Correctable Write

Index-4Data return format, 2-19Data status errors, 2-41, 6-73Data Status Error bit, 7-8Data Syndrome 0 bit, 7-9Data Syndrome 1 bit, 7-9Data Syndrome 2

Index-5Drive TLSB Bad bit, 7-81DRIVE_BAD, 7-81DRIVE_CONWIN, 7-81DRIVE_RUN, 7-81DSE, 7-8DS0, 7-9DS1, 7-9DS2, 7-9DS3, 7-9DTag CPU bit, 7-48DTag Data Ent

Index-6False arbitration, 2-7, 2-14Fatal Data Transmit Check Error bit, 7-8Fatal No Acknowledge Error bit, 7-10Fault Disable bit, 7-52FAULT_DIS, 7-52F

Index-7ICCNSE register, 7-117ICCWTR register, 7-127ICC and IDP internal illogical errors, 6-77ICC CSR Bus Par Err bit, 7-118ICC Internal Error bit, 7-

Index-8I/O Control Chip Node-Specific Error register,7-117I/O Ctrl Chip Window Transaction register,7-127I/O Data Path Diagnostic register, 7-133I/O D

Index-9Memory mapping register error, 3-18, 6-71Memory Mapping Register Error bit, 7-10memory module capacity, 7-105Memory module, overview, 1-4Memory

2-10 TLSB Bus Figure 2-2 Address DecodeWhen a physical address is presented to the bank decode logic, all valid ad-dress bits, as determined by the

Index-10CPU Module Configuration, 7-52Data Diagnostic, 7-106Data Mover Command, 7-72Data Mover Destination Address, 7-76Data Mover Source Address, 7-7

Index-11Self-Test Error in MDI0 bit, 7-96Self-Test Error in MDI1 bit, 7-96Self-Test Error in MDI2 bit, 7-96Self-Test Error in MDI3 bit, 7-96Self-Test

Index-12TLEPMERR register, 7-59TLEP_VMG register, 7-62TLESR0-3 registers, 7-26TLFADR0-1 registers, 7-24TLILID0-3 registers, 7-30TLINTRMASK register, 7

Index-13UECC, 7-27Uncorrectable Data Error bit, 7-10Uncorrectable ECC Error bit, 7-27Unexpected acknowledge, 6-71Unexpected Acknowledge bit, 7-8Unexpe

TLSB Bus 2-112.2.3.4 Bank Available StatusTLSB_BANK_AVL indicates that a bank is available for use. When notasserted, no requests except Wri

iv2.2.4.3 Address Bus Transactions ... 2-122.2.4.4 Module Transactions...

2-12 TLSB Bus2.2.4 Address Bus ArbitrationThe TLSB bus has demultiplexed address and data buses. These buses op-erate independently and are relat

TLSB Bus 2-13Consequently, the priority of any device will eventually bubble up to thehighest level. The no-op command is the only non-data

2-14 TLSB Busin a request cycle, that CPU must take part in the following arbitration cy-cle even if the bus is no longer required. If the device wi

TLSB Bus 2-15CPUs can request the bus without first checking that the bank is busy. Ifthe bank does turn out to be busy, this is considered

2-16 TLSB Busin subsequent CSR accesses, and it is not ready to source or accept data, itcan delay asserting TLSB_SEND_DATA, or it can assert TLSB_H

TLSB Bus 2-17• No-op command cyclesTwo signals are used to provide parity protection on the address bus dur-ing all command cycles. TLSB_CMD

2-18 TLSB BusWrite Bank UnlockUsed by the I/O port to complete a Read-Modify-Write. Writes the dataspecified by the address and bank number and unl

TLSB Bus 2-192.2.7.3 Back-to-Back Return DataTwo memory read transactions are returned back to back as follows.TLSB_SEND_DATA for the first t

2-20 TLSB BusIf one CPU drives TLSB_HOLD while another drives TLSB_SHARED orTLSB_DIRTY, the second keeps driving TLSB_SHARED andTLSB_DIRTY. TLSB_HO

TLSB Bus 2-21 Table 2-5 TLSB Data Wrapping2.2.8.6 ECC CodingData is protected using quadword ECC. The 256-bit data bus is dividedinto four

v2.4.3.8 Multiple Address Bus Errors... 2-382.4.3.9 Summary of Address Bus Error

2-22 TLSB BusCheck bits are computed by XORing all data bits corresponding to columnscontaining a one in the upper table and inverting bits <3:2&

TLSB Bus 2-23TLSB_SHARED is valid when driven in response to Read, Read BankLock, Write, and Write Bank Unlock commands. Nodes may, therefor

2-24 TLSB Bus2.2.9 Miscellaneous Bus SignalsSeveral signals are required for correct system operation. They are:• TLSB_DATA_ERROR — A hard or sof

TLSB Bus 2-25and allows the CPUs asserting TLSB_LOCKOUT to complete their bus ac-cess without interference.TLSB_LOCKOUT is asserted for one c

2-26 TLSB Bus Figure 2-4 TLSB CSR Address Bit Mapping2.3.1 CSR Address Space RegionsA total of 1 terabyte of physical address space can be mapped

TLSB Bus 2-27 Figure 2-5 TLSB CSR Space MapAll TLSB node CSRs are 32 bits wide, except the TLMBPR and TLRDRDregisters, which are wider. Data

2-28 TLSB Bus Table 2-7 TLSB Node Base AddressesTable 2-8 shows the mapping of CSRs to node space and broadcast spacelocations. Locations are give

TLSB Bus 2-29 Table 2-8 TLSB CSR Address MappingAddress Name MnemonicModules That Implement BB+000BB+040BB+080BB+0C0BB+200BB+240BB+280BB+2C0

2-30 TLSB Bus2.3.2 TLSB MailboxesCSRs that exist on external I/O buses connected to an I/O port (or anotherI/O module implementing mailbox registe

TLSB Bus 2-31Table 2-9 describes the mailbox data structure. Table 2-9 Mailbox Data StructureThe mailbox address is a 64-byte aligned memory

viChapter 4 Memory Subsystem4.1 Internal Cache...

2-32 TLSB Busstructure. Software may choose to reuse mailboxes (for example, multiplereads from the same CSR), or it may maintain templates that a

TLSB Bus 2-33predictable as the value has no significance. The I/O node may choose notto acknowledge the command and save data bus cycles.Th

2-34 TLSB Bus2.4.1 Error CategoriesError occurrences can be categorized into four groups: • Hardware recovered soft errors • Software recovered so

TLSB Bus 2-352.4.2 Error SignalsThe TLSB provides two signals for broadcasting the detection of an error toother nodes. All nodes monitor

2-36 TLSB Busevery cycle, enabled solely by the driven assertion value. For example,TLSB_CMD_ACK is assertion checked to verify that if this node at

TLSB Bus 2-37When a commander node issues a CSR access command but does not re-ceive acknowledgment, it sets <NAE> in the TLBER registe

2-38 TLSB BusBER<BAE> is set if the Write Bank Unlock command appears on the busbefore the second data cycle of the preceding Read Bank Lock c

TLSB Bus 2-39 Table 2-10 Address Bus Error Summary2.4.4 Data Bus ErrorsData bus errors are either ECC-detected errors or control errors.

2-40 TLSB Bus2.4.4.1 Single-Bit ECC ErrorsA single-bit error on a memory data transfer is detected by a node’s ECCchecking logic. The decision to c

TLSB Bus 2-41This timeout can be disabled by software. The <DTOD> bit in the TLCNRregister prevents <DTO> from setting. It does

vii5.2.2.3 CSR Write Data ECC Check ... 5-105.2.2.4 Forcing Write Errors for Dia

2-42 TLSB BusSystem fatal data bus errors are cumulative. Should a second system fatalerror occur, TLSB_FAULT is asserted a second time. If a fata

TLSB Bus 2-43Some errors are more important to software than others. For example,should two correctable data errors occur, one during a writ

2-44 TLSB BusThe CSR registers contain information about the error. The commander’sTLBER register contains either correctable or uncorrectable erro

TLSB Bus 2-452.4.6.2 Write ErrorsWrite data operations involve a minimum of two nodes. The commanderissues the command and transmits the dat

2-46 TLSB Busstill cause interrupts. Interrupts for correctable read data errors shouldalso be disabled, as read errors will result from not correct

CPU Module 3-1Chapter 3CPU ModuleThe CPU module is a DECchip 21164 based dual-processor CPU module. Each CPU chip has a dedicated 4-Mbyte mo

3-2 CPU Module Figure 3-1 CPU Module Simple Block Diagram3.1.1 DECchip 21164 ProcessorThe DECchip 21164 microprocessor is a CMOS-5 (0.5 micron) su

CPU Module 3-3• On-chip 8-Kbyte virtual instruction cache with seven-bit ASNs(MAX_ASN=127).• On-chip dual-read-ported 8-Kbyte data cache (imp

3-4 CPU ModuleTo facilitate the multiplexing of the 256 bits of TLSB data to the 128 bitsrequired by the DECchip 21164 interface, longwords (0,4), (

CPU Module 3-5• A set of module-level parallel I/O ports for functions such as LED status indicators and node identification • Two serial I/O

viii6.5.3 Error Detection Schemes ... 6-346.6 Hose Interface ...

3-6 CPU Module Table 3-1 Directly Addressable Console Hardware3.3 CPU Module Address SpaceDECchip 21164 supports one terabyte (40 bits) of address

CPU Module 3-7from cache or the TLSB as shown in Table 3-2. Bit <4> specifies which16-byte portion of the 32-byte subblock is returne

3-8 CPU Module3.3.2 I/O SpaceThe I/O space contains the I/O window space, TLSB CSR space, moduleGbus space, and DECchip 21164 private CSR space.

CPU Module 3-93.3.2.3 Gbus SpaceThe Gbus is the collective term for the FEPROMs, console UARTs, watchchip, and module registers. All Gbus re

3-10 CPU Module3.4 CPU Module Window Space SupportCSRs that exist on some external I/O buses are accessed through windowspace transactions. Rather

CPU Module 3-11 Table 3-4 Decrement Queue Counter Address AssignmentsFor window space reads, the I/O port issues the write to the DecrementQ

3-12 CPU Module Table 3-5 PCI Address Bit Descriptions3.4.4.1 Sparse Space Reads and WritesIn PCI sparse space, 128 bytes of address are mapped to

CPU Module 3-13data issued by DECchip 21164 is transmitted on the TLSB, along with allthe INT4 mask bits. The I/O port pulls the appropriate

3-14 CPU ModuleDense PCI memory space is longword addressable only. You cannot writeto individual bytes. You must do longword writes. You can do

CPU Module 3-15are reported to DECchip 21164 through system machine check interrupts(IPL 1F hex - SYS_MCH_CHK_IRQ). The interrupt causes th

ixChapter 7 System Registers7.1 Register Conventions ...

3-16 CPU Module• Data Timeout Error (DTO)• Data Status Error (DSE) • Sequence Error (SEQE)• Data Control Transmit Check Error (DCTCE)• Address Bus T

CPU Module 3-173.5.2.1 Transmit Check ErrorsA node must check that its bus assertions get onto the bus properly byreading from the bus and co

3-18 CPU Module3.5.2.3 No Acknowledge ErrorsWhenever a commander node expects but does not receive an acknowledg-ment of its address transmission as

CPU Module 3-193.5.4 Multiple ErrorsThe error registers can only hold information relative to one error. It isthe responsibility of softwa

Memory Subsystem 4-1Chapter 4Memory SubsystemThe memory subsystem consists of hierarchically accessed levels that re-side in different locati

4-2 Memory Subsystem4.1.3 Second-Level CacheThe second-level cache (S-cache) is a 96-Kbyte, 3-way set associative,physically addressed, write-back

Memory Subsystem 4-34.2.2 B-Cache TagsMany locations in memory space can map onto one index in the cache. Toidentify which of these memory

4-4 Memory Subsystem Figure 4-3 Cache Index and Tag Mapping to Block Address (16MB)4.2.3 Updates and InvalidatesIf a block is shared, and a CPU wa

Memory Subsystem 4-5 Table 4-1 B-Cache StatesA block becomes valid when the block is allocated during a fill. A block be-comes invalid when