Digital Equipment Corporation DV11 User Manual

DV11 communications multiplexer user's manual

MODEM CONTROL INTERRUPT SET-UP MODEM CONTROL UNIT MODEMS I DATA LINES TO ---------------~-----REMOTE MODEMS VI ::l CD DATA HANDLING Z ...------4 ::

DVll COMMUNICATIONS MULTIPLEXER USER'S MANUAL EK-DVII-OP-OOI Reader's Commen Your comments and suggestions will help us in our continuous ef

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The Received Character (RC) Silo is a first-in, first-out storage buffer with a capacity of 128 characters. When a character is received by the

Title GENERAL PDP-II Peripherals Handbook PDP-II Instruction List Logic Handbook Introduction to Minicomputer Networks Binary Synchronous Communicatio

Figure 1-2 DVII Communications Multiplexer Parity Generation and Detection Odd, Even, or None Modems Accommodated Synchronous modems (Bell System 2

This chapter provides information for interfacing, installing, and testing the DVII Communications Multiplexer. Interfacing considerations are

DVlls should be connected ahead of all Massbus devices on the Unibus and behind unbuffered NPR devices such as RK05s. DVlls have placement requi

Table 2-1 EIA Electrical Specifications Driver output logic levels with 3K to 7K load Driver output voltage with open cir-cuit Driver output impedance

~.2 UNPACKING AND INSPECfION \fter unpacking, check that the following parts are )resent for the basic DVII-AA unit: I D-AD-7010834-0-0 Logic Assembly

2.3.1 Unibus Cable Interconnections The DV II is shipped with one M920 Unibus Con-nector (placed in slot 9 as shown in the module utili-zation p

1 2 3 4 5 6 M920 M7836 M7837 M7838 M78391 ~+~~r M7833 CABLE UNIBUS ALU UNIBUS ROM MUX MUX A CONNECTOR AND DATA RAM LINE LINE NOTE 3 TRANSFER AND AND C

DV11 communications multiplexer user's manual EK-OV11-0P-001 digital equipment corporation • maynard, massachusetts

A12 A11 A10 A09 AOS ON=O A07 OFF = 1 A06 A05 A04 UNUSED 7414-3 Figure 2-3 DVII M7836 Module - Device Address Selection Switches 2-7

7414-1 Figure 2-4 DVll M7837 Module - Interrupt Vector Address Selection Switches for DVll Data Handling Section 2-8

INTERRUPT VECTOR ADDRESS (002 -DOS) Jumper Bit W1 DOS W2 002 W3 003 W4 006 W5 007 W6 005 W7 004 Jumper In = 1 W18 W12 W17 W13 W5 W1 W2 W7 W3 W4 W6 Fi

Table 2-2 Device Address Switches M7807 Jumper W8 WI4 Wll W9 WIO WI6 WI7 WI3 WI2 WIS M7836 Switch I 2 3 4 S 6 7 8 9 Device Address Bit AI2 All A

M7837 Switch Address Bit Notes: 1. 2. 3. Table 2-3 Vector Address Switches for Data Handling Section (Vector Addresses are Modulo 10) 1 2 3 4 5 6 D08

M7807 Jumper Address Bit Table 2-4 Vector Address Jumpers for Modem Control Unit (MCU Vector Addresses are Modulo 4) WI· WS W4 W6 W7 W3 DOS 007 006 DO

Table 2-4 (Cont) Vector Address Jumpers for Modem Control Unit (MCU Vector Addresses are Modulo 4) M7807 Jumper WI· WS W4 W6 W7 W3 W2 Vector Address B

SWITCH PACK 2 Baud rate and Duplex Select SWITCH PACK 4 Sync Character A 7414-5 Figure 2-6 Location of Sync Switches on M7839 Module 2-14 SWITCH PACK

Table 2-5 Synchronous Parameter Selection Switches Switch Function Parameter Name Pack Number Setting Internal Baud 1200 Baud Select B S2 3 ON Rate

Table 2-5 (Cont) Synchronous Parameter Selection Switches Switch Function Parameter Name Pack Number Setting Sync Req. (cont) 2 SYNC REO. 1 SYNC

Copyright © 1976 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without not

2.5 SYSTEM CHECKOUT Turn on the power. Toggle in the Bootstrap and load the Absolute Loader (if not already done). The addresses and contents of

NOTES: D!STR !BUT!ON PANEL EIA CONNECTOR P. GND EIA XMIT DATA 00 EIA RCV DATA 00 RTS 00 CTS 00 S GND CARRIER 00 (202 SEC TX gg) NEW --1------0--0--.-

This chapter contains all information required for controlling operation of the DVII Communications Multiplexer by means of the PDP-ll program.

W I N Type Directly Addressable (Modem Con-trol Unit) Directly Addressable (Data Handling Section) Indirectly Addressable (Secondary ) Table 3-1 Funct

Table 3-1 (Cont) Functions of DVII Programmable Registers Type Name FUllctiOi lS Functional C ategory Table Indirectly Transmitter Alternate Current C

3.1.2 Control Table The control table contains the control bytes fetched from core memory by the DV II each time a character is received or is to be t

... 1_---&. _______ .L...-_"""'"--_--'--_--L.._---"_x ... 1 TRANSMIT CONTROL BVTE 07 DISCARD/STORE E

3.1.3.2 Accessing Secondary Registers -The Sec-ondary Register Selection Register (SRS) provides for PDP-II program access to the secondary re

3.1.4.3 Control Byte Inhibit -For protocols such as DDCM P, which do not require arbitrary mode changes within a data block, provision has been made

The DV 11 provides such a double-register system in the form of two registers for storage of transmitter current addresses and two registers for sto

CHAPTER 1 1.1 1.2 1.2.1 1.2.1.i 1.2.1.2 1.2.2 1.3 1.3.1 CHAPTER 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.4.1 2.1.4.2 2.1.4.3 2.1.5 2.2 2.3 2.3.1 2.4 2.4.1 2.

SYSTEM CONTROL REGISTER (SCR) 77 5000 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 NPR STATUS INT. OVFLOW INT. NPR OVFLOW REC.INT RECVR.INT RO

'5 I R I I \ VALID ENTRY IN 00-" '5 '4 '3 12 I J\ UNUSED SPECIAL FUNCTIONS REGISTER (SFR) 775012 ROM DATA REGISTER CONT

LINE STATUS REGISTER (LSR) 775022 (FOR SYNCHRONOUS LINE CARDS) 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 I I R I R R R '-J UNUSED RING

Table 3-2 System Control Register Bit Assignments Bit(s) Designation Function Read/Write 00 Microprocessor GO When set to one, enables the Microproc

Bit(s) 09 10 11 12 13 14 IS Designation (Maintenance) NPR Status Overflow (Vector B) Master Clear NPR Status Overflow Interrupt Enable NPR Status Inte

Bit(s) Designation 00-01 (Maintenance) 02-03 -04-05 Extended Address Read 06 -07-09 (Maintenance) 10 Sync Select 11,12 (Maintenance) 13 Receiver Enab

Table 3-3 (Cont) Line Control Register Bit Assignments (For Synchronous Line Cards) Bit(s) Designation Function Read/Write 15 Control Strobe When set

Bit(s) Designation 00,01 (Maintenance) 02,03 -04,05 Extended Address Read 06,07,08 -09,10 Register Selection Code 11-14 Asynchronous Line Card Registe

Bit(s) 09,10 11 12 13 14 15 Designation Table 3-4 (Cont) Line Control Register Bit Assignments (For Asynchronous Line Cards) Function Asynchronous Lin

Bit(s) 09,10 11,12 13 14 15 09,10 11-14 Designation Table 3-4 (Cont) Line Control Register Bit Assignments (F or Asynchronous Line Cards) Function Asy

3.1.4.3 3.1.4.4 3.1.4.5 3.1.4.6 3.1.4.7 3.1.5 3.1.5.1 3.1.5.2 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.

Bit(s) 11-14 (Cont) 15 Designation Table 3-4 (Cont) Line Control Register Bit Assignments (For Asynchronous Line Cards) Function Asynchronous Line Car

Bit(s) Designation Table 3-4 (Cont) Une Control Reg~ter Bit Assignments (For Asynchronous Line Cards) Function Read/Write Asynchronous Line Card Main

Table 3-S Receive Function Interrupt Conditions (For Synchronous Line Cards) Code Set in RIC 12-IS IS I 14 I 13 I 12 Meaning 0 0 0 0 Special Charact

Code Set in RIC 12-15 15 14 13 12 1 1 1 0 1 1 1 1 Code Set in RIC 12-1 5 15 14 13 12 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 Table 3-

Code Set in RIC 12-1 5 IS 14 13 I 12 o o o o o o o o o o o o o o Table 3-6 (Cont) Receive Function Interrupt Conditions (For Asynchronous Line Card

Table 3-7 Transmit Function Interrupt Conditions Code Set in NSR OS-II Meaning Transmiiter principal current address specified a non-existent memory l

Bit(s) 00-03 04 05 06 Designation LINE (Line Number) BUSY SCAN EN (Scan Enable) INTER EN (Interrupt Enable) Table 3-8 Control Status Register Bit Assi

Table 3-8 (Cont) Control Status Register Bit A~ignments Bit(s) Designation Function Read/Write 07 DONE Set to one whenever a transition occurs on a R

Table 3-8 (Cont) Control Status Register Bit Assignments Bit(s) Designation Function Read/Write 12 DSR Set to 1 whenever an ON to OFF or OFF to ON Re

Table 3-9 Line Status Register Bit Assignments Bit Designation Function Read/Write 00 LINE EN When set to 1 for the line selected by bits 0-3 of the

CONTENTS (Cont) APPENDIX A PDP-II MEMORY ORGANIZATION AND ADDRESSING CONVENTIONS APPENDIX B PROTOCOLS FOR BINARY SYNCHRONOUS COMMUNICATIONS APPENDIX

Table 3-9 (Cont) Line Status Register Bit Assignments Bit Designation Function Read/Write 06 CO (Carrier On) (detected) Set to 1 whenever the CO line

TRANSMITTER PRINCIPAL CURRENT ADDRESS (0000) 15 TRANSMITTER PRINCIPAL BYTE COUNT (0001) 15 1 - NORMAL BYTE COUNT 0· MARKED BYTE COUNT TRANSMITT

TRANSMITTER CONTROL TABLE BASE ADDRESS (1000) 15 RECEIVER CONTROL TABLE BASE ADDRESS (10011 15 LINE PROTOCOL PARAMETERS (1010) 15 LINE STATE

3.3.3 Transmitter Alternate Current Address (0010) The Transmitter Alternate Current Address register has exactly the same function as the Transmi

3.3.9 Transmitter Control Table Base Address (1000) The Transmitter Control Table Base Address second-ary register contains the 18-bit address of t

Table 3-10 Line Protocol Parameters Secondary Register Bit Assignments Bit(s) Designation Function Read/Write 00 Idle Mark When set to one, causes th

Bit(s) 00 01 02 03 Designation Receiver Active Receiver Resynchronize Transmitier Go Transmitter Underrun Table 3-11 Line State Secondary Register Bit

Table 3-11 (Cont) Line State Secondary Register Bit Assignments Bit(s) Designation Function Read/Write 04 Transmitter Non-Set to one by the Micropr

Bit(s) 11-12 13-15 Bit(s) 00 01 02 03-04 Table 3-11 (Cont) Line State Secondary Register Bit Assignments Designation Next Receive Mode on Marked Byte

Table 3-12 (Cont) Line Progress Secondary Register Bit Assignments Bit(s) Designation Function Read/Write 05 Expect BCCI (Not intended for access by t

Table No. 34 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 TABLIS (Cont) TItle Line Control Register Bit ASSignments (For Asynchronous Line Cards)

Table 3-12 (Cont) Line Progress Secondary Register Bit Assignments Bit( s) 07 08-09 10 11-12 13-15 Designation Resynchronization Rag Expected Send BCC

Bit(s) 00 01 02 03 04 05-07 Table 3-13 Control Byte Bit Assignments Transmitter Control Byte Unused (to effect symmetry) Send Data Link Escape Next: W

3.5 DVll INITIALIZATION DV II initialization consists of setting up the DVII line modems and the DVII Data Transfer Section. 3.5.1 Line Modem Set-U

3.6.1 Originating and Answering Calls The Control Status Register (CSR) arid the Line Stat-us Register (lSR) are provided to enable the PDP-II program

3.6.4 BISYNC Implementation BISYNC implementation software is considered in three functional groups: control tables, interrupt service routin

TRANSPARENT o INITIAL TRANSPARENT TRANSMISSION TRANSPARENT DATA TRANSMISSION 2 END OF TRANS-PARENT BLOCK NON-TRANSPARENT 3 INITIAL NON-TRANSPARENT TRA

Table 3-14 Transparent Data Transmission Control Data Buffer Control Byte Directives Stuf Send BCC After No. Contents Current A DLE? This Character? 2

YES o WAITING FOR MESSAGE 2 NON-TRANSPARENT DATA RECEPTION ·RECEIVED THE BCC TRANSITION TO TRANSPARENT RECEPTION NO YES 3 TRANSPARENT DATA RECEPTION 4

Mode 1 (Transition to Transparent Reception) I n this mode, the system initializes for the reception of transparent text. Mode I is entered only from

1. SET PRlt"CIPAL XMIT REGS WITH HEADER BUFFER AD· DRESS & B.C. 2. SET BIT TO SEND BCC WHEN B.C.-O 1. SEND BUFFER 2. SET BIT TO SEND BCC WHE

A y SET TO RECEIVE eIDCT., DV'T"~~ "'lUI oJ UI Ir;..~ - - DV11 INTERRUPT BOOTSTRAP (DLEI OR DATA (SOHI GET CHARACTER COUNT AND BUI

The PDP-II memory is organized into 16-bit words consisting of two 8-bit bytes. Each byte is addressable and has its own address location: low bytes a

~ 08107 ~ 16 BIT DATA WORD HIGH BYTE LOW BYTE 00000 1 000000 r---------~------~ 000003 000002 757777 760001 -----------757776 760000 *777777 777776 1

000001 000003 157777 160001 HIGH BYTE I I --LOW BYTE --.. I 000000 000002 157776 160000 *'77777 177776 1 I USER ADDRESS SPACE 'I :g~~~:~:~~

APPENDIX B PROTOCOLS FOR BINARY SYNCHRONOUS COMMUNICA.TIONS A protocol is a set of rules which govern the sequenc-ing, identification, and synchroniza

B.2 DATA AND CONTROL CODES The purpose of a data channel is to transfer data, unaltered, from a transmitter station (master) to a receiver sta

Bit Position P 6 5 4 3 2 0 01aracter 1 0 0 0 Character 2 0 0 0 0 0 Character 3 0 0 0 0 0 Character 4 0 0 0 0 0 LRC-8 BCC 0 0 0 0 0 Figur

CHAPTER 1 INTRODUCTION AND GENERAL DESCRIPTION 1.1 PURPOSE AND SCOPE This manual is intended to provide operational pro-gramming information for th

Table B-1 BSC Data Channel Control Codes Control Code Mnemonic SYN SOH STX ITB ETB ETX EDT ENQ ACKO/ACKI WACK NAK DLE RVI TTD DLE EDT Meaning Synchron

BB COUNT FLAG RESPONSE SEQUENCE ADDRESS CRC-1 DATA CRC-2 SOH (ANY NUMBER OF 8-BIT 14 BITS 2BITS 8 BITS 8 BITS 8 BITS 16 BITS CHARACTERS UP TO 214 )

0) CD @ @ TERMINAL Sends a STRT (START) message which means: "I want to begin sending data to you and the !i:equence numher of my first message

B.4.6 Synchronization OOCM P achieves synchronization through the use of two ASCII SYN characters preceding the SOH, ENQ, or OLE. It is not neces

APPENDIX C GLOSSARY OF TERMS AND ABBREVIATIONS A CK -Acknowledgment ACK O. ACK I (Affirmative Acknowledgment) -These replies (DLE sequence in Binary

Concentrator - A communications device that pro-vides a communications capability between many low-speed, usually asynchronous channels, and one or

EBCDIC - Extended Binary Coded-Decimal Inter-change Code. An 8-bit character code used primarily in I BM equipment. The code provides for 256 differ-

lYon-Processor Request (N PR) - High priority data transfers to the PDP-II Processor. These are direct memory access type transfers, and are honored b

Synchronous Idle (S Y N) -Character used as a time fill in the absence of any data or control character to maintain synchronization. The sequence of