Digital Equipment Corporation PDP-9 Specifications

alMml digihl equipmentcorpomtion

to identify an interrupt, since the interrupt servicing hardware selects and begins executing the appropriate service routine. The device

SUBROUTINE CALL: JSR reg,dst 1 JSR Jump to SubRoutine (dstb (tmp), 0%) J (PC> + (w3), Ww) + (PC) SUBROUTINE RETURN: RTS reg RTS ReT

RTI IOT RESET ReTurn from Interrupt 000002 4 d / / 4.8 t Pa f (W Input/Output Trap 000004 d/v’/ 8.9 (PSI 4 s (PC) 4, (20) + (PC), (22

/ 94

APPENDIX R-ADDRESSING SUhMlARY ADDRESSING. ‘MODES. S,C or’ dst GENERAL REGISTER ADDRESSING Mode 0 ’ 1 2 5 6 7 Description register register defe

SUBROUTlNE CALL: JSR r*g.dsl SUBROUTINE RETURN; RTS rr9 0 , 0 I, 0 I I 2 t I I I 0 II 1 r*g II 15 3 2 0 . SINGLE OPERAND GROU

0 4 10 14 i: 30 34 40 44 50, 1 54 z 70 74 . . . . . . 400 . . . * . . PROCESSOR STACK PROGRAM AND DATA RESIDENT SYSTEM SOFTWARE (ABSOLUTE LOADER

177560 TELElYP;- KEYBOARD AND PUNCH DEVCE STATUS AND EUFFER REGISTER -’ . . . * 177576 17-7600 . RESERVEP FOR EXPANSION OF PROCESSOR REG

. APPENDIX l+UNlBUS OPERATIONS There are ‘six bus operations: four to effect data transfers, on9 to transfer bus control, and one to

5. 6. Master sees SSYN and waits 75 nanoseconds, minimum (data des- kewing + internal gating deskewing). Master.strobes data, drops MSY

\ NOTES: 1. Step 1 of the next-data transfer-may begin at step 5 of the current DATO or DATOB. 2. Step .2 of the next data trans

in the field. In case maintenance is required, defective System Units can be replaced with spares and operation resumed within a f

INTR-lNTerRupt This bus operation is initiated by a master immediately after receiving bus control to effect a program interrupt in th

pitig BBSY); If control is given up actively, only NPR~requests will‘be honored during the interrupt sequence of.updating the PC and

’ I c The PDP-11 provides Direct Device Addressing. All memory-and devices on the Unibus are directly addressable and may be op erated

All PDP-11 processors, memories and peripherals are electrically and mechanically modular subsystems .supported in System Units. which

I CHAPTER i SYSTEM INTRODUCTION SYSTEM DEFINITION Digital Equipment Corporation’s PDP-11 is a 16.bit, general-purpose, parallel- logic compu

Dvnamlc Master-tive #?e!&eM astar-slave relationships are dynamic. The ,processor, for example, may p&s bus control to a disk. T

Read-only core memory (ROM) is available in 1,024 16 bit-word segments. The access time of the ROM is 500 nanoseconds. Memory is a

NPR Requeata-NPR data transfers can be made between any two peripheral devices without the supervision of the processor. Normally, N

Priorities permitting, the processor relinquishes the bus to that device. When the device has control of the bus, it sends the proc

service routine is begun. Note that those operations all occur auto- matically and that no device-polling is required to determine

CHAPTER 3 ADDRESSING jdODES‘ Most data in a program is structured in some way-in a table, in a stack, in a table of addresses, op

Copyright 1969 by Digital Equipment Corporation PDP is a registered trademark of Digital Equipment, Corporation The material in this ha

Deferred register addressing may also be selected in PAL-11 by the form OPR (R). INDEXED AD~RE&G-T~IZ general fegisters may be used

(decrement by two) address and-uses the new contents of the general reg- ister as the operand address. Instructions of the form -0P

tion word may be taken as the address of an operand by specifying deferral in immediate mode addressing. That is, instructions of

and is followed by index words and immediate operands for the source and destination address fields as appropriate. Source address

CHAPTER 4 INSTRUCTION SET This chapter Presents the order code for the PDP-11. Each PDP-11 instruc- tion is described in terms of fiv

Arithmetic Operations- Operation: (src) + (dst) Condition Codes: Z: set if (src) = 0; cleared otherwise N: set if (src) < 0; clea

Description: Adds the source operand to the destination operand and stores the re&lt at the destination address. The original co

COMParo CMP rrc.dst 2.3ur’ 01 2 WC dst I I I I 1 1 1 I I I t (5 12 11 6 5 0 .Operation: (src) - (dst) [in detail, (src) + - (dst)

Bll Test BIT rrc,dst .2.9*** * 0, 3 WC I I I I I I dd , I I 1 I . 15 12 11 6 5 0 Operation: (src) A (dst) Condition Codes: Z:

TABLE OF CONTENTS . CHAPIER 1 lNTRODUCTlOR PDP-11 SYSTEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .:.. . . . . . . . . . . .

gbnpk corldttbnrit Bran&es-Conditioned branches combine in one instruc- tion a conditional sMp, unconditional branch sequence. . Timing f

Operation: lot + (PC) if N = 0. Description: Tests the state of the N-bit and causes a branch if N is,clear. BPL is the compleme

largest . . . . . . . . . . . . . . . . . . . . . . . . . . . 077777 077776 positive . . . 000001 000000 177777 177776 negative lQo00l smallest 100

Branch on Less than or Equal(Z*ro) BLE lot 1.5~~. 2.6~ 01 to, I ‘31 14 offset I t I I I i5 07 0 Operation: lot + (PC) if Z v (N

Branch on LOwn BLO IOC t.5 YS, 2.6~s Offset t 1 0, 1 , 3 , 1 4 I I I I I 1.1 95 e 7 0 Operation: lot + (PC) if C = 1 Desc

address. A “boundary error” condition will result when the processor at- tempts to fetch an instruction from an odd address. Deferre

ReTurn from Sutwoutine 3.5&S 15 I 3 2 0 Operation: (reg) + (PC) T (ret3 Condition Codes: not affected Description: Loads content of

The instruction INC Rl increases the contents of Rl by 1 and the instruction CLR RO zeroes the register RO 2. Saving and restoring

At this point execution of RTS PC returns control to the main program. A character is typed in DECTY by loading the teleprinter b

TYPFIN: HALT TYPOUT: JSR R5, TOLER - . WORD ARRAY . WORD -LENGTH . WORD HILIM TYPCHK: . WORD LOLIM BEQ TYPFIN JSR R5, SAVE MOV -(RO),

. . DOUBLE OPERAND-INSTRUCTIONS ... i.. ... 17 Arithmetic Operations ... 1. ...

DECrment DEC drt 2.3~ 01 10, I 15‘ I 13, I I I I I 15 6 5 ‘0 Operation: (dst) - 1 + (dst) Condition Codes 2: set if the resul

Multiple Precision Operations-It is sometimes convenient to d6 arithmetic on operands considered as multiple words.‘The PDP-11 makes spe

ROtaA Right ROR dst 2.3~ dst 01 lOI I I 6 I .I 0 , I I I I 1 15 6 5 0 Condition Codes: Z: set if all bits of result = 0; c

- Arithmetic Shift Right ASR dst 2.3 us dst 01 , 0, 1 , 6, 1 , 2 , I t I e I 15 6 5 0 Condition Codes: Z: set if the result

Double precision norma’lization proceeds similarly: , DNORM: ASL A0 ; double precision left shift ROL Al BEQ DZERO ; high order result

Operation: (src) + (dst) Condition Codes: Set on the byte result as in MOV Description: Same as MOV instruction. The MOVB instructi

LNLINE is the Length of uNpacked LINES. The routine requires 24 words. EDIT: MOV # INSTRING, RO ; set up input byte pointer MOV

~. NEGote Byte NEGB -dst 23ns I Ii, dst ‘I 101 I 141 I I I t I5 6 5 0 l -. Operation: -(dst) + (dst) ; in detail, - (dst) f. 1

, . mtate Left Byte ROLB drt ’ ~ 2.3~1 Q dst 1 , , 0 I 6 3 I t 1 I I .I 1 1 1 ’ ’ 1 15 6 5 0 Operation: as in ROL on byte operand

Combinations of the above set or clear operations may be ORed together to form new instruction mnemonics. For example: CLCV = CLC

. \ TELETYPE CONTROL (MODEL KLll) ... Teletype Control ...

EMulotw Traps EMT xycx 9.9 us 1 XXI ‘I 101 ,4, 0, , , , 1 , , 15 9 7 0 Operation: (PS) J, SP WI J SP (30) + PC (3?) + PS Condi

R.Turn from Interrupt RTI 4.Bus / 01 ,o, I IO, I 101 I 101 I a21 IS 0 Operation: SP T (PC), SP t (PS). Condition Codes: loaded fr

An instruction that set the T-bit-Since the T-bit was already set, Settiflg it again has no effect. An instruction that caused an In

CHAPTER 5 ADDRESS ALLOCATION The PDP-11 provides for a very flexible addressing structure. Both 16-bit words and 8-bit bytes can be di

in Figure 5-1. Three areas of addresses of particular interest to the Pro- grammers are: 1) Interrupt and Trap VeMors; 2) Processor

CHAPiER 6 PROGRAMMING OF PERIPHERALS Programming of peripherals is extremely simple in the PDP-11-a special class of instructions to de

devices. Many devices will require less than sixteen status bits. Other devices will require more than sixteen bits and therefore wi

acter. Incrementing the PRS will set bit 0 and cause one character to be read. The instruction INC PRS performs that function. MOV

A tvoical set might be: _. 1. Control-and status register 2. Memory address register 3. Word count register 4. Device address register

ReTurn fmm Interrupt instruction is used to reverse the action of the interrupt sequence. The top two words on the stack are popp

UNIBUS CONTROL ’ ... ... Priority Arbitration ...

The DIGITAL M225 module contains 8 high speed general-purpose registers. The M225 general registers provide program flexibility when u

CHAPTER 7 TELETYPE (MODEL LT33-DC/DD) The standard Teletype Model 33 ASR (Automatic Send-Receive) can be used to type in or print ou

Teletype unit to release the tape feed latch. When releasea the latch mechanism stops tape motion only when a complete character h

Registers Teleprinter Status Word (TPS) 7 6 2 I * 1 0 0 1 L I- IN-f EN6 L MAINTENANCE READY CONTROL Bit 2 MAINT Maintenance function which

by setting a DONE bit. If the interrupt is enabled and the interrupt is granted, the processor traps to location 70, and may immed

Registers Paper Tape Punch Status Word (PPS) Bit 6 7 15 INT ENB READY ERROR O-No Interrupt; l-Attached fo priority iflterrUFt system. (Note

ENVIRONMENTAL 55”-100°F 20% -95% RH (without condensation) ~- MODEL DESCRIPTION POWER REQUIREMENTS PC11 Reader, Punch & Control 115+10% 6

CHAPTER 8 -~ DESCRIPTION OF THE UNIBUS Communication between all system units in a PDP-11 configuration is done by a single common bus

the bus to communicate with other devices, call,ed slaves, on the bus. An example of this relationship is the processor (master) f

. scFrwAF& AOORESS HAROWARE ADDRESS oooo#O-017777 trt 4K MEMORY BANK 02CWO-037777 El oooooo-own7 02ooOO-037777 2nd 4K MEMORY 0Aw I I I I t4

INSTRUCTION FORMATS ._.___...___... 95 APPENDIX C-ADDRESS MAP . . . . . . . . . . . . . . . . . . .

device. A data transfer from processor to memory (always a slave) is “data out,” and a transfer from memory to processor is “data

I instruction sequence will leave 10027 in location 500. In binary form, this coding appears as: 1000: 105210 ;INCB @RO 1002: 062710 ;A

MASTER \ SLAVE OPERATION: DAl-0 A.C,D MSYN ‘4 rg------ SSYN A’C’D 3 I SSYN Figure 8-4(a) The flow of signals for DATI is shown in Figure

cessor status register. These three bits set a priority level that inhibits granting of bus requests-on lower levels. Second, bus re

by negating BBSY. Bus control will then pass to either a device that was selected in the meantime by another PTR sequence or bac

program would set certain function bits in the disk’s command and status register that specify a read or write function. For this

, ,I ; . . The plug-in console board with modular construction is supplied in the basic 11/20 configuration. In addition to aiding p

CHAPTER 9 Interfacing A typical device bus interface as shown in Figure 9-l is composed of five major components: 1). Registers; 2),

I I I I I I I I L- M930 --- i WI-- -J DRIVER Rl , R2=190fi 5% 1/4W R3. R4 = 390A 5% iI4W Figure 9.2 Typical Unibus Line Information is

Ml05 ADDREsS SELECTOR Tho ‘Ml05 Address Selector as shown in Figure 9-6 is used to provide gating signals for up to four device r

The PDP-11”is available in two versions-PDP-ll/lO and PDP- 11/20. The basic PDP-ll/lO contains 1,024 words of read only memory in conjunct

. Figure 9.5 M785 Unibus Drivers and Receivers A00 is used for byte control. A01 and A02 are decoded to provide one of four addr

EXT. CAP I -J f , 1 1 SELECT 2 H EH t SELECT 4 H SELECT 6 Ii A62L J I A61 L AmL I OUTHl6HH GIL OUT LW Ii CaL a IN tl Figure 9.6 Ml0

-i I . . L--- -- ------2 Figure 9.7 Typical Peripheral Device Regker 74

In addition to two Master Control circuits, a third logic network provides the necessary signals and gating to perform the INTR bu

, DEVICE CONTROL LOGIC The type of control logic for a peripheral depends on .the nature of )h” device. Digital offers a wide line

CHAPTER 10 CONFlGURATtON AND INSTALLAflON PLANNING MODULAR CONSTRUCTlbN Physically, the PDP.11 is composed of a number of System Units.

+ For 115 V standard, 3prong; U-ground, 15-ampere connectors + For 230 V pigtail leads on one end 3. Cooling Fans 4. Filter 5. Programme

. Approximate Weight-90 Itis. (including CP, cdnsole and AK core) Power-12OV zflO%,47-63 Hz 6 amps. single phase @All-C5 and H720-A)

PDP-11 TABLETOP UcFENSfdh MOUNTING BOX (BAll-EC)-The tabletop Extension Box is supplied, when ordered, for mounting of up to 6 additiona

10. H955)-D Mounting Panel Doors 11.. H952-B Stabilizer Feet 12. #7406782 Kick Plate 13. #7005909 Power Distribution Panel (ac ?rrd dc,

CHAPTER 1 INTRODUCTION This publication is a handbook for Digital Equipment Corporation’s PDP-11. It provides a comprehensive overview

UNIBUS MODULE (M920)-The M920 is a double module which connects the Unibus from one System Unit to the next within a Mounting Box

. INSTALLATION .PROCEDlJRE The PDP-11 is crated for shipment to the customer site to prevent damage. Installation is provided by DEC

The PDP-11 has adopted a moddlar packaging approach to allow custom configuring of systems, easy expansion and easy servicing. . . 8

CHAPTER 11 PAPER TAPE SiFTWARE SYSTEM‘ ’ PAPER TAPE SOFTWARE SYSTEM (PTS) PTS is a compatible group of software packages designed to aid

Debugging operations alternate between commands to ODT and the running of the program to be debugged. Breakpoints are set in the u

CHAPTER 12 1. ’ THE OPERATOR’S CONSOiE ‘The PDP-11 Operator’s Console has been configured to achieve convenient control of the system

3. Bus-indicates that a peripheral is controlling the bus. It is lit when BBSY (Bus Busy) is asserted, unless the processor (which

When the system is running a program, the LOAD ADDR, EXAM, and DE- POSIT functions are disabled to prevent disrupting the,program.

other lights; (Fetch, Execute, Source, Destination; the.Address lights, and the Address and Data registers) will be flickering. If th

APPENDIX A-PDFIi INSTRUCTION REPERTOIRE Mnemonic instruction Codes Operation OP Code ZNCV DOUBLE OPERAND GROUP: OPR scr;dst MOV(B) MOVe (B