Digital Equipment Corporation AlphaPC64 User's Guide

Digital Alpha VME 4/224 and4/288 Single-Board ComputersUser Guide and Technical DescriptionOrder Number: EK–DAVME–TD. B01This manual describes the Dig

11.2 Module Reset ... 11–1312 Console Primer12.1 About the Console ... 12–112.1.1 Console

Local Area Network Address ROM TestLocal Area Network Address ROM TestThis diagnostic tests the integrity of the Local Area Network (LAN) addressROM,

Local Area Network Address ROM TestFigure 4–2 LAN Address ROM FormatAddress Octet 0Address Octet 1Address Octet 2Address Octet 3Address Octet 4Address

NCR 53C810 PCI-SCSI I/O Processor TestsNCR 53C810 PCI-SCSI I/O Processor TestsThese tests check the NCR810 SCSI controller chip. The tests do not requ

NCR 53C810 PCI-SCSI I/O Processor TestsNCR810 Command/Status Register TestThis test writes, reads, and compares all of the NCR810 command/status regis

NCR 53C810 PCI-SCSI I/O Processor TestsNCR810 Interrupt TestThis test verifies the interrupt connection between the NCR810 and the SIOcontroller to the

Watchdog Timer Interrupt TestWatchdog Timer Interrupt TestThis test verifies the functionality of the watchdog timeout by its ability to handlea user p

VME Interface TestsVME Interface TestsThese tests verify the VME interface logic on the Digital Alpha VME 4module, including the VME interface process

VME Interface TestsVME Scatter-Gather RAM TestThis test verifies the integrity of the scatter/gather RAM by performing write,read, and verify of variou

4.4 Initialization SequenceThe diagnostic test sequence for a full power-on reset and initialization is shownin Figures 4–3, 4–4, and 4–5.Figure 4–3 S

Figure 4–4 Console POST FlowsBLEDDisplayNotesConsole testConsole testConsole testConsole testConsole testConsole testConsole

echo . . . ... 13–30eval . . . ... 13–32examine ...

Figure 4–5 Console POST FlowsWatchdog TestCLEDDisplayNotesConsole testConsole testConsole testML013410VIP-VIC TestsConsole PromptHI4–32 D

5System Address MappingThis chapter describes the mapping of the 34-bit processor physical address spaceinto memory and I/O space addresses. It also i

Figure 5–1 System Bus Address Map1 E000 00001 E000 1FE01 E001 00001 E001 1FE01 E002 00001 E002 1FE0VMEEthernetSCSISIOPMC Module1 C000 0000Programmedb

Table 5–1 System Bus Address Space DescriptionsysAdr<33:32>sysAdr<31:28> Address Space Description00 xxxx Cacheable memoryspaceAccessed by

Table 5–1 (Cont.) System Bus Address Space DescriptionsysAdr<33:32>sysAdr<31:28> Address Space Description10 xxxx PCI sparse memoryspace12

5.1.4 DECchip 21071-DA CSR Space (0x1A0000000 to0x1AFFFFFFF)The DECchip 21071-DA responds to all accesses in this space. Section 7.4specifies the regis

Figure 5–2 shows the translation of system bus addresses to PCI bus I/Oaddresses. Table 5–2 shows how the byte enable bits and PCI ad<2:0> arege

Table 5–2 PCI Sparse I/O Space Byte Enable GenerationLengthCPUAddress<6:5>CPUAddress<4:3>PCI ByteEnable1PCI ad<2:0>Byte 00 00 1110 C

5.1.7 PCI Configuration Space (0x1E0000000 to 0x1FFFFFFFF)A read or write access to this space causes a configuration read or write cycle onthe PCI. The

Table 5–4 PCI Address Decoding for Primary Bus Configuration AccessesDevice Number (sysAdr<20:16>) PCI ad<31:11>00000 0000 0000 0000 0000 0

sp ... 13–100start . . ... 13–101stop . . . ...

Peripherals that integrate multiple functional units (for example, SCSI, Ethernet,and so on) can provide configuration spaces for each function. Bits a

5.1.8 PCI Sparse Memory Space (0x200000000 to 0x2FFFFFFFF)Access to PCI sparse memory space can have byte, word, tribyte, longword, orquadword granula

Figure 5–3 PCI Memory Space Address Translation01 00000Non-Zero00000LJ03938A.AILength in BytesLongword Address33 29 2832 31 08 07 0506 04 03 02 000133

Table 5–5 PCI Sparse Memory Space Byte Enable GenerationLengthCPUAddress<6:5>CPUAddress<4:3>PCI ByteEnable1PCI ad<2:0>2Byte 00 00 11

One bit pair of cpucwmask<1:0>, <3:2>, <5:4>, and <7:6> must have a valueof 01 (binary). The other fields must be 00. The locat

• On write transactions, ad<4:2> is generated from cpucwmask<7:0>. If thelower longword is to be written, ad<2> is 0; if the lower l

Table 5–6 PCI Target Window EnablesPCI_MASK<31:20>1Window Size Value ofn20000 0000 0000 1 MB 200000 0000 0001 2 MB 210000 0000 0011 4 MB 220000

Figure 5–4 PCI Target Window Compare SchemeLJ-03955.AI31nn20 19 13 12 0031nn20OffsetHitXXXComparePeripheral Page NumberPCI AddressPCI BaseRegister31nn

Table 5–7 PCI Target Address Translation—Direct MappedPCI_MASK<31:20> Translated Base <32:5>0000 0000 0000 T_BASE<32:20>:PCI ad<1

Figure 5–5 Scatter-Gather Map Page Table Entry in MemoryLJ03956A.AI63 32MBZ31 20 000121Page Address <32:13> ValidMBZThe size of the scatter-gath

2–15 Connecting the PMC I/O Companion Card... 2–262–16 Installing the PMC I/O Companion Card ... 2–273–1 Controls and Indicators . ...

Table 5–8 Scatter-Gather Map AddressPCI_MASK<31:20>Scatter-GatherMapTable SizeScatter-GatherMap Address<32:3>0000 0000 0000 1 KB T_BASE<

Figure 5–6 Scatter-Gather Map Translation of PCI Bus Address to System BusAddressLJ03957A.AI31n13 12 0005 04OffsetPeripheral Page NumberPCI Address33

6Cache and Memory SubsystemThe cache and memory subsystem serves as the memory controller and thesystem bus (sysBus) controller.Figure 6–1 Cache and M

Figure 6–2 Address and Data Paths of Cache and MemoryML013273 21071-BA032 Bits32 Bits32 Bits32 Bits32 Bits32 Bits32 Bits32 BitsmemData <127:0>Me

Figure 6–3 21071-CA Block DiagramML013275TagCompareAddressGeneration tagadr<31:17>adr<33:5>WriteBufferAddress Row andColumnGenerati

6.1 System Bus InterfaceThe CPU, DECchip 21071-CA, PCI host bridge, cache, and memory communicatewith each other through the system bus. The system bu

6.2 Bcache ControlFigure 6–4 shows the implementation of a cache subsystem with a 2 MB cache.Figure 6–4 Cache Subsystem fora2MBCacheML013276Bcache SIM

6.3.1 Memory OrganizationA bank of memory is one width of DRAMs, 128 bits, implemented with DIMMs.The DECchip 21071-CA supports one or two banks of DR

6.3.2 Memory Address GenerationEach bank has a programmable base address and size. The incoming physicaladdress is compared with the memory ranges of

6–20 Refresh Timing Register: 0x180000220 ... 6–296–21 Block Diagram of the DECchip 21071-BA ... 6–307–1 PCI Host Bridge ...

6.3.7 Presence Detect LogicThe DECchip 21071-CA supports loading the status of 32 presence detect bitsfrom the memory configuration registers 0 to 3 an

Table 6–1 identifies all banks; only Bank 0 and 1 are used.Table 6–1 CSR Register Addresses for DECchip 21071-CAAddress16Register Name1 8000 0000 Gener

Table 6–1 (Cont.) CSR Register Addresses for DECchip 21071-CAAddress16Register Name1 8000 0A40 Bank 2 configuration register1 8000 0A60 Bank 3 configura

6.6 Description of CSRs6.6.1 General Control RegisterThe general control register contains status information that affects the memory,cache, and syste

Table 6–2 General Control RegisterField Name Type Description<15:14> Reserved MBZ —<13> BC_BADAP RW, 01Bcache force bad address parity. Wh

Table 6–2 (Cont.) General Control RegisterField Name Type Description<5> BC_EN RW, 0 Bcache enable. When clear, the L2 cache isdisabled and the

Figure 6–7 Error and Diagnostic Status Register: 0x18000002015 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00LJ-04179.AIWRPENDLDXLLOCKPASS 2MBZCREQCAUSE

Table 6–3 (Cont.) Error and Diagnostic Status RegisterField Name Type Description<8:6> CREQCAUSE RO Cycle request caused error. Indicates theDMA

6.6.3 Tag Enable RegisterThe tag enable register (TAGEN), shown in Figure 6–8, indicates which bits ofthe cache tag are compared to sysadr<33:5>

Table 6–4 Cache Size Tag Enable ValuesTAGEN<15:0>ComparedBits Cache Size0000 0000 0000 00001None 4 GB1000 0000 0000 0000 <31> 2 GB1100 000

9–14 82C54 Timer Data Access ... 9–289–15 Timer Clocking... 9–319–16 Timer Interrupt Status Register .

Table 6–5 Maximum Memory Tag Enable ValuesTAGEN<15:0>ComparedBits Memory Size1111 1111 1111 11101<31:17> 4 GB0111 1111 1111 1110 <30:17

Figure 6–9 Error Low Address Register: 0x18000008015 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00LJ-04181.AIERR_LADR<20:5>6.6.5 Error High Addre

Figure 6–11 LDx_L Low Address Register: 0x1800000C015 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00LJ-04183.AILDXL_LARD<20:5>6.6.7 LDx_L High Add

Figure 6–13 Presence Detect Low-Data Register: 0x18000028015 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00LJ-04186.AIPRES_DET<15:0>6.6.8.2 Presen

Figure 6–15 Bank 0 Base Address Register: 0x18000080015 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00LJ-04188.AIS0_BASEADR<33:23>MBZThe base addr

Table 6–6 Configuration Register for Banks 0 and 1Field Name1Type Description<15:9> Reserved MBZ —<8:6> S0_COLSEL RW Column address selecti

Table 6–6 (Cont.) Configuration Register for Banks 0 and 1Field Name1Type Description<4:1> S0_SIZE RW Bank size in Mbytes. Indicates the size of

The description of the parameters also indicates the corresponding DRAMparameter. Bank 0’s timing register A is shown in Figure 6–17 and is definedin T

Table 6–7 (Cont.) Timing Register AField Name Type Description<6:4> S0_COLSETUP RW, 0 Column address setup (tASC) to first CASassertion and write

Table 6–8 Timing Register BField Name Type Description<15:14> Reserved MBZ —<13:11> S0_WHOLD0COL RW, 1 Write hold time from column address

11–11 VIC Error Group ICR . . . ... 11–1011–12 VMEbus Interrupter ICR ... 11–1011–13 VIC Error Group Interrupt

Figure 6–19 Global Timing Register: 0x18000020015 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00LJ-04193.AIMBZGTR_MAX_RAS_WIDTHGTR_RPTable 6–9 Global Ti

The refresh timing register is shown in Figure 6–20 and is defined in Table 6–10.Figure 6–20 Refresh Timing Register: 0x18000022015 14 13 12 11 10 09 0

Table 6–10 (Cont.) Refresh Timing RegisterField Name Type Description<0> DISREF RW, 0 Disable refresh. Refresh operations are notperformed when

6.7.1 Memory Read BufferThe memory read buffer stores data from memory before the data is sent to theCPU or returned to DMA in the DMA read buffer. Ea

6.7.5 Memory Write BufferThe memory write buffer has four entries for each chip. Each entry has fourlongwords and corresponding ECC bits. The system b

7PCI Host BridgeThe 21071-DA chip is the bridge between the PCI local bus and the system bus,as shown in Figure 7–1.Figure 7–1 PCI Host BridgePCI Host

Figure 7–2 DECchip 21071-DA Block DiagramML0134604-EntryDMA WriteAddressFIFO DMA Read AddressDMA WriteAddressPCI ad<31:0>ReadBypassMUX3 LW

7.1.2 Buffering System Bus TransactionsWrite-and-run I/O write transactions use a 1-entry write buffer. One I/O readtransaction is initiated by the CP

7.2.3 Burst Length and Prefetching for PCI busOn write transactions directed toward main memory, the PCI host bridgesupports a maximum burst length of

7.3.3 Data CoherencyThe two agents that must synchronize their data transfers are the CPU and anyPCI device. The PCI host bridge maintains data cohere

3–1 Controls and Indicators . ... 3–23–2 Environment Variable Summary . . ... 3–44–1 Console Diagnostic Tests ...

7.3.4 InterruptsWhen the PCI host bridge has errors to report, it uses the int_hw0 signal tointerrupt the CPU. It does not distinguish between hard an

7.3.7 Retry TimeoutThe PCI host bridge implements a timeout mechanism to terminate CPU-initiatedtransactions that do not complete on the PCI bus becau

Table 7–1 (Cont.) DECchip 21071-DA CSR AddressesAddress16Register Name1 A000 0040 System bus error address register (SEAR)1 A000 0060 Dummy register 1

Table 7–1 (Cont.) DECchip 21071-DA CSR AddressesAddress16Register Name1 A000 03E0 TLB 7 data register1 A000 0400 Translation buffer invalidate all reg

Figure 7–3 Diagnostic Control/Status Register: 0x1A000000031 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01

Table 7–2 (Cont.) Diagnostic Control/Status RegisterField Name Type Description<17:16> D_BYP<1:0>RW, 0 Disable read bypass. Controls the o

Table 7–2 (Cont.) Diagnostic Control/Status RegisterField Name Type Description<14> IPTL RWC, 0 Invalidate page table lookup. This bit is set wh

Table 7–2 (Cont.) Diagnostic Control/Status RegisterField Name Type Description<6> LOST RWC, 0 Lost error. This bit is set by a 21071-DA errorco

Figure 7–4 PCI Error Address Register: 0x1A000002031 30 08 07 06 05 04 03 02 01 00LJ-04197.AIPCI_ERR<31:0>09101112131415161718192021222324252627

Table 7–4 System Bus Error Address RegisterField Name Type Description<31:3> SYS_ERR<33:5> RO System bus error address. Stores the address

9–2 Module Configuration Register... 9–79–3 DIMM Identification . . . ... 9–99–4 Presence Detect ...

Table 7–5 Translated Base Registers 1 and 2Field Name Type Description<31:9> T_BASE<32:10> RW Translated base. If scatter-gather mappingis

Table 7–6 (Cont.) PCI Base Registers 1 and 2Field Name Type Description<19> WENB RW, 0 Window enable. When clear, the PCI targetwindow is disabl

Table 7–7 PCI Mask Registers 1 and 2Field Name Type Description<31:20> PCI_MASK<31:20> RW PCI mask. This field specifies the size ofthe PCI

Table 7–8 Host Address Extension Register 1Field Name Type Description<31:27> EADDR<4:0> RW, 0 Extension address. This field is used as the

7.5.11 PCI Master Latency Timer RegisterThe PCI master latency timer register defines the latency timer period. Define anonzero value during system confi

Figure 7–13 TLB Tag Registers 0 Through 7: 0x1A0000200 to 0x1A00002E031 30 08 07 06 05 04 03 02 01 00LJ-04205.AIPCI_PAGE<31:13>EVAL0910111213141

Table 7–12 TLB Data Registers 0 Through 7Field Name Type Description<31:21> Reserved MBZ —<20:1> CPU_PAGE<32:13> RO CPU page. Bits &

8PCI busThe PCI bus is the base for the I/O subsystem. All I/O components are connectedby the 32-bit, 5 V only, PCI implementation and are called PCI

Figure 8–1 PCI Bus and Interfaces to the I/O SubsystemPCI HostBridge(21071-DA)PCI toNbusBridgeEthernetControllerSCSIControllerPCI-VMEBridgePCI

8.1 Ethernet ControllerThe physical connection to the network is the Ethernet twisted-pair connectorlocated on the front panel of the module.The Ether

11–1 Table of CPU Interrupt Assignments ... 11–111–2 VIC64 Chip Interrupt Ranking . . . ... 11–611–3 VME IRQ ICR Priority Assig

Figure 8–2 PCI Configuration RegistersI/O Base Address (CBIO)Memory Base Address (CBMA)ReservedReservedReservedN/S (=Not Supported)ReservedRese

Table 8–1 Ethernet Controller CSRsRegister Meaning AddressCSR0 Bus mode register xxxx xx00HCSR1 Transmit poll demand xxxx xx08HCSR2 Receive poll deman

8.1.4 Ethernet AddressThe Ethernet ID address for the Digital Alpha VME 4 assembly is stored in anon-board SROM, a 20-pin socketed PLCC. The Ethernet

8.2.2 SCSI IDThe default SCSI ID is 7. You set the SCSI ID by writing the SCSI controller’sSCID register (offset 0x04). To do this, use the following

Figure 8–4 PCI Configuration BlockI/O Base Address (SCSI_IO_BASE)Memory Base Address (SCSI_MEM_BASE)ReservedReservedN/S (=Not Supported)Reserved

Table 8–2 SCSI Controller CSRsLabel R/W Description OffsetSCNTL0 R/W SCSI Control 0 00SCNTL1 R/W SCSI Control 1 01SCNTL2 R/W SCSI Control 2 02SCNTL3 R

Table 8–2 (Cont.) SCSI Controller CSRsLabel R/W Description OffsetDCD R/W DMA Command 27DNAD R/W DMA Next Add for Data 28-2BDSP R/W DMA SCRIPTS Pointe

8.3 PCI I/O Companion CardYou can connect an optional PMC I/O companion card to the I/O module. Thiscard contains a 21052 PCI-to-PCI bridge chip and t

9NbusThe Nbus is a special case of an ISA bus. The Nbus is a simple 8-bit data,16-bit address, nonmultiplexed resource bus that interfaces with the PC

First Printing, July 1996Revised, September 1996Printed in U.S.A.The information in this document is subject to change without notice and should not b

• NVRAM• Interval timersThe bottom 1 MB in PCI sparse memory space is mapped onto the Nbus for useby the flash ROM.These address regions are negatively

Figure 9–2 SIO Configuration BlockReservedPCI ControlMEMCS# Control (not used)ISA Addr Decode (not used)ReservedMEMCS# Attributes (not used)Res

9.1.1.2 ISA Controller Recovery Timer RegisterThe ISA controller recovery timer register (offset +4Ch) is one of two bytewideregisters used as the Nbu

Register CPU Address Nbus OffsetModule display control 1 C001 0000 800Module configuration 1 C001 0020 801Interrupt register 1 1 C001 0040 802Interrupt

Figure 9–3 Module Display Control Register31 08 07 06 05 04 03 02 01 00ML013287Brightness ControlDisplay CharacterDon't CareMOD_DISP_REG :The dis

This read-only register contains information relating to module revision, CPUspeed, and SCSI options. The information read from this register is hardw

Table 9–2 (Cont.) Module Configuration RegisterField Name Type Description<6:5> CPU ID RO Determine the speed of the CPU according to the followi

These registers are read-only. The values are loaded from memory DIMMs,identified in Table 2–8 at power-up. A complete description of the memoryDIMMs i

Figure 9–7 Memory Identification Register31 08 07 06 05 04 03 02 01 00ML013316Bank 1 DRAM1 ID1Bank 1 DRAM1 ID0Don't CareMEM_ID_REG :Bank 1 DRAM0 I

Table 9–4 Presence DetectBit PD Bit Description<3:0> PD 4-1PD Bits4321Configuration(Parity/ECC)DRAMOrganizationREAddressCEAddressRefreshPeriods (

PrefacePurpose of this ManualThis manual describes the Digital Alpha VME 4 module. It provides configurationand installation procedures and describes t

Table 9–5 ID BitsBit ID Bit Description<6,4,2,0> ID 0 Used to define memory DIMM configuration (see Table 9–6).<7,5,3,17> ID 1 Sets the refr

These registers are read/pseudowritable registers located at a fixed address onNbus in PCI I/O address space. Register 1 is located in Nbus offset 0x80

Table 9–7 (Cont.) Reset Reason RegistersField Name Type Description<2> VME reset 0x80A : R/W toclear0x80E : ReadOnly82E : R/W to setIf set, it i

Figure 9–9 Module Control Register 131 08 07 06 05 04 03 02 01 00ML013289Timer 0 Mode EnableUndefinedDon't CareMOD_CNTRL_REG_1 :Watchdog Reset En

Table 9–8 (Cont.) Module Control RegisterField Name Type Description<5> Watchdog TimerReset EnableWhen 0, watchdog timer expiration has noeffect

Table 9–9 Bcache Size and Speed Decode<2> <1> <0> Bcache Size Bcache Speed0 0 0 Disables Bcache0 0 1 512 KB 15 ns0 1 0 2 MB 12 ns0 1

Figure 9–11 Flash ROM Layout/AddressingML013291ROM_BASE_ADDR :512 KB512 KB1 MB1 MB1 MB<00><01><10><11>Start of Console Firmwar

Channel B is uncommitted and uninitialized by system firmware.For more information about these serial lines, see Chapter 2.9.4.2 Super I/O Register Add

Table 9–10 (Cont.) Super I/O Register Address Space MapAddress OffsetRead/WritePhysicalAddress RegisterCOM2 Serial Port Registers2F8-R 0DLAB=0 1 C000

Table 9–10 (Cont.) Super I/O Register Address Space MapAddress OffsetRead/WritePhysicalAddress RegisterParallel Port Registers3BC-R/W 1 C000 7780 Data

• Chapter 3, Operating the Digital Alpha VME 4 Computer, explains how touse the Digital Alpha VME 4 module’s controls and indicators, introducesconsol

Table 9–12 lists the register and memory addresses for the keyboard/mousecontroller.Table 9–12 Keyboard and Mouse Controller AddressesOffset Physical

9.6.1 TOY Clock Timekeeping RegistersCPU Address: 0x1C0100000 - 0x1C01FFFE0Nbus offset: 0x8000 - 0xFFFFTime information is contained in eight 8-bit re

Field Register Description<7> TOY_BASE_ADDR+09 Enable Oscillator bit.Enables/disables the TOY clock chip’s internaloscillator. Use it to conserv

Table 9–14 (Cont.) TOY Clock Command RegisterField Name Type Description<2> Not used<3> Watchdog TimerEnableR/W<4> Pulse/Level O/P R

Table 9–15 Timer Interface RegistersFieldRegisterTMR_BASE_ADDR = 4000 Description<7:0> TMR_BASE_ADDR+00 Timer#0 RegisterTMR_BASE_ADDR+04 Timer#1

Table 9–16 Interval Timing Control RegisterField Name Type Description<7:6> Specifies which timer is to be configured by thiscontrol byte. When se

Figure 9–14 82C54 Timer Data AccessML013296Data Rd/Wr (byte)Mode 01 or 11?Mode 11?MSBNo"Signal Done"YesLSBData Rd/Wr (byte)YesNo9.7.2 Timer

interrupt request (IRQ). The IRQ can be dismissed by an access to the timerinterrupt status register.9.7.3 Timer ModesOf the six timer modes of which

The timer output is initially high. When the timer value is written, theoutput is driven low. The counter decrements to 0 where it drives the outputhi

9.7.4 InterruptsThe expiration of timers #0 and #2 are recorded in a timer status register. Theasserted state of either or both of the timer status bi

ConventionsThis section defines terminology, abbreviations, and other conventions used inthis manual.Abbreviations• Register accessThe following list d

The Timer IRQ line is asserted for a low-to-high transition of a timer’s output pinwhen that timer is enabled in the CSR to cause an interrupt. The in

Table 9–18 (Cont.) Timer Interrupt Status RegisterField Name Type Description<1> Timer #2 statusWhen clear, the IRQ is dismissed. The bitis clea

(general-purpose registers (GPRs), and so forth) at the time the watchdog timerexpires before the full hardware reset.Watchdog timer operation is cont

Table 9–19 Watchdog Timer TOY Clock Command RegisterField Name Type Description<0> Not used<1> Watchdog timer flag R/W<2> Not used<

9.9 Nonvolatile RAMDigital Alpha VME 4 offers just under 32 KB of battery backed-up on-boardSRAM. The RAM is provided by the DS1386 chip and is held n

10VME InterfaceThe VME interface handles the VMEbus and its interactions with the PCI bus.This chapter describes the functions of the VME interface, w

The VME interface serves the following purposes:• As a VMEbus master, it controls PCI bus-to-VMEbus, or outbound,transactions• As a VMEbus slave, it h

Figure 10–2 shows a mapping of Window_1 and Window_2.Figure 10–2 Mapping Window_1 and Window_2512 MBWindow_164 MBWindow_2S/G 255S/G 0ML013378Each page

Figure 10–3 Mapping Pages From PCI to VMEML0133774 GB Mem Space2048 x 256KPages512 MBPCIA32VMEA24A16Scatter-GatherMapping10.1.1 Outbound Scatter-Gat

Figure 10–4 Outbound Scatter-Gather Entry31 08 06 05 04 00ML013328Function Code <2:1>Address Size <1:0>o/b VME PageRMWSwap <2:0> Mod

CautionCautions indicate potential damage to equipment or loss of data.Data Field SizeThe term INTnn, where nn is one of 2, 4, 8, 16, 32, or 64, refer

10.1.1.1 Address ModifierThe scatter-gather entry has two fields that provide the address modifier usedin the master VMEbus transfer. The address size (A

The two accesses are handled as an indivisible sequence on the VMEbus byacquiring VMEbus ownership for the current access and holding it until another

Because the VMEbus specification prohibits crossing any 256/2 KB boundaries,any DMA must split into a number of bus transfers. At the interval betweent

• Source address• Destination addressThe mapping of PCI memory to VMEbus addresses is handled as usual throughthe scatter-gather mapping mechanism, ho

Incoming slave accesses are mapped and controlled by two incoming scatter-gather maps:• For A32 accesses, a Digital Alpha VME 4 system occupies up to

VIF_ABR (VME_IF_BASE + 184) defines the base address of the Alpha VME 4system in each VMEbus address space as shown in Figures 10–7 and 10–8.Figure 10–

10.2.2 Inbound Scatter-Gather EntriesThe inbound scatter-gather RAM format is shown in Figure 10–9 and describedin Table 10–3.Figure 10–9 Inbound Scat

Table 10–3 (Cont.) VME AddressField Name Description<13:12> PageMonitorSpecifies how a Digital Alpha VME 4 system checks the scatter-gather entry

Table 10–5 VME Interface Processor Page Monitor CSRField Name Description<2:0> Monitor 1 Number of access to page.<3> Overflow Overflow for

Because the global switches are meant to be issued to several modules, the slavetargets of a global switch access do not acknowledge the cycle, but ra

Names and SymbolsThe following table lists typographical conventions used for names of variousitems throughout this manual.Items ExampleBits sysBus<

Table 10–6 (Cont.) Interprocessor Communication Register Map Through VIF_ABR<byte 1>+ RegisterInterprocessor communication registers (ICR)07 8-b

Table 10–6 (Cont.) Interprocessor Communication Register Map Through VIF_ABR<byte 1>+ RegisterInterprocessor communication module switches (ICMS

10.3.1 Arbitrating the VMEbus10.3.1.1 Requesting the VMEbusThree arbitration schemes — priority, round-robin, and single-level — areachieved by a comb

Table 10–7 Arbiter/Requester Configuration RegisterField Name Description<3:0> FairnesstimeoutThe fairness timeout field accepts the following val

In addition to these four bus release modes, the scatter-gather RMW bit (RMC)can be used to force Digital Alpha VME 4 to hold ownership of the VMEbus

Table 10–8 (Cont.) VIC Release Control RegisterField Name Description<7:6> Release protocol Specifies the release mode, according to the followin

10.3.3.2 VMEbus Transfer TimersWhen enabled, the VME interface starts the transfer timer whenever the dataphase of a cycle is signaled (DSx* asserting

Table 10–9 (Cont.) VMEbus Transfer Timeout RegisterField Name Description<7:5> VMEbustimeoutSpecifies the timeout, according to the following val

Figure 10–14 VIC Interrupt Request/Status Register31 08 07 06 05 04 03 02 01 00ML013345IRQ7IRQ6Don't CareVME_IF_BASE + 80 :IRQ5IRQ4IRQ3IRQ2IRQ1En

Figure 10–15 VMEbus Interrupt Vector Base Registers31 08 00ML013346Status/ID VectorDon't CareA local interrupt can be generated to the CPU by the

SyntaxThe following syntax elements are used throughout this manual. Do not type thesyntax elements when entering information.Element Example Descript

10.4 Byte SwappingThe Digital Alpha VME 4 interface provides hardware to support byte-swappingfor transfers to and from the VMEbus. Four modes of swap

Figure 10–17 Swap ModesMode 0: No swapD0D321110010000011011LittleEndianByte Add.Mode 1: Byte swapD0D321110010000011011Mode 3: Longword swapD0D321110

Figure 10–18 Big Endian VME Byte Lane FormatsML013371byte 3byte 2byte 1byte 0byte 3byte 2byte 1byte 0byte 2byte 1byte 0 byte 2byte 1byte 1 byte 3byte

Table 10–13 PCI BE# to Local A1,0 and SIZ1,0 Translation for Various SwapModesPCIBE#<3:0>Mode 0No SwapA1,0SIZ1,0Mode 1Byte SwapA1,0 SIZ1,0Mode 2

Table 10–14 Local Bus A1,0 and SIZ1,0 to PCI BE# TranslationLocal BusA1,0 SIZ1,0 DataMode 0BE#Mode 1BE#Mode 2BE#Mode 3BE#00 00 D[31:0] 0000 0000 0000

The windows defined by these registers must not overlap each other. Thefollowing sections describe these registers and the region of address space they

The scatter-gather RAM is an 32K n longword page in memory space. The top27 bits are read/write; the remaining 5 bits are MBZ. Scatter-gather RAM isno

DMASICRBits 2-0 Local IPL setting for end of DMA interrupt.Bits 6-3 Reserved, must read as 1s.Bit 7 End of DMA interrupt mask bit.LICR1-7Bits 2-0 Loca

Bits 7-2 User defined. Combines with ICMS switch number to provide vector.LIVBRBits 1-0 Read only.Bits 7-2 User defined. Combines with LIRQ number to pr

Bit 0 Set to include VMEbus acquisition time in local bus timeout.Bit 1 When VME interface is used as system controller, this bit is set toindicate ar

Operations that produce UNPREDICTABLE results might also produceexceptions.An occurrence specifed as UNPREDICTABLE might happen or not basedon an arbi

Bits 6,5 VMEbus request level.Bit 7 Arbitration mode.AMSR Defines response top and generation of user-defined address modifiercodes.BESR All 8 bits are fl

Bits 3-0 Interleave period. Recommend a value of 0xF.Bit 4 Data direction bit: 0=write, 1=read.Bit 5 MOVEM enable. Recommend this be clear.Bit 6 BLT w

Table 10–16 (Cont.) VME_IF_BASE +A8 VIC_BTDR Block transfer definition registerAC VIC_ICR Interface configuration registerB0 VIC_ARCR Arbiter/requester

Table 10–16 (Cont.) VME_IF_BASE +128 VIP_IBISGMSK VME interface processor inbound internal scatter-gatherentry mask12C VIP_IBISGWORD VME interface pro

10.7 VME Subsystem Restrictions (as of 03-Jun-94)This section describes limitations on the use of the VME subsystem due tooutstanding hardware constra

11System Interrupts11.1 System InterruptsFigure 11–1 shows a schematic overview of the interrupt structure in the DigitalAlpha VME 4 system. Most inte

Figure 11–1 Block Diagram of the Interrupt LogicVIC_IPL2VIC_IPL1VIC_IPL0VME ResetInterval Timer IRQPeriodic RT TimerTimer #1 IRQ1 ms Heartbeat

Each interrupt can be individually masked by setting the appropriate bit in theinterrupt/mask register. Interrupts generated by the VMEbus subsystem a

Figure 11–4 Interrupt/Mask Register #307 06 05 04 03 02 01 00ML013319PMC1 IRQ CPMC0 IRQ C804 :PMC1 IRQ BPMC0 IRQ BSCSI IRQETHER IRQSIO IRQVME IPL3Figu

11.1.2.1 Basic OperationThe VIC64 chip handles 19 interrupt sources. Each of these can be individuallyprogrammed to any of the seven IPLs in the contr

For More InformationDocument Order Number CompanyCY7C9640 Specification CypressSemiconductorCorp.DECchip 21040–AA Specification EC–N0752–72 Digital Equi

Table 11–2 VIC64 Chip Interrupt RankingRANK Interrupt Description CSRs19 DC7407 Error VIC_LICR7, VIC_LIVBR18 VME Interface Status/Error VIC_EGICR, VIC

Each of the these interrupt sources has an associated ICR that allows theinterrupt to be programmed with an individual IPL or to be disabled. Figure 1

Figure 11–9 VME IRQ* ICRs31 08 07 06 03 02 01 00ML013305DisableDon't CareEncoded Priority 1-7Table 11–3 VME IRQ ICR Priority AssignmentsAddress R

• DMA completion• VMEbus IACK cycle in response to a VMEbus interrupt generated by anAlpha VME systemThese conditions are divided into three cases.The

Figure 11–11 VIC Error Group ICR31 08 07 06 05 04 03 02 00ML013310ACFAIL* Interrupt MaskWrite Post Fail Interrupt MaskDon't CareArb. Timeout Inte

Figure 11–13 VIC Error Group Interrupt Vector Base Register31 08 07 06 05 04 03 02 01 00ML013312User Programmable Vector-Base000 ACFail001 Write Post

11.1.4.2 NMI Status and Control RegisterFigure 11–14 shows the NMI status and control register.Figure 11–14 NMI Status and Control Register31 08 07 06

Table 11–4 (Cont.) NMI Status and Control Register BitsField Name Type Description<3> HALT Enable R/W When set to a one, HALTs are disabled and

The VMEbus SYSRESET* assertion generates a module reset only if Switch 3is closed. This prevents a module configured as a VME system controller fromloc

12Console PrimerThis chapter describes the Digital Alpha VME 4 console and explains how to usebasic commands to perform console tasks.The console achi

1Product Overview1.1 Product DescriptionThe Digital Alpha VME 4/224 and 4/288 MHz single-board computers are basedon the 21064A Alpha processor chip.

• Self-test diagnostics and extended functional diagnostics.You use UNIX command methods to combine these tools to solve complexproblems. The UNIX com

12.1.3 Shell OperatorsThe UNIX command line makes use of some Bourne shell operators to complete acommand. In OpenVMS, some commands take parameters.

Table 12–2 (Cont.) Console Shell OperatorsOperator Name Description(),{} Grouping Shows which commands are grouped together incomplex command lines. T

• if command_sequencethen command_sequence[ elif command_sequence then command_sequence ][ else command_sequence ]fiConditional branching in if, while,

Command Description Exampleshow pal Displaysversionnumber ofPALcodeVMS PALcode V5.56-4, OSF PALcode X1.45-8show device Displaysknowndeviceson systemdk

>>> help examine depositNAMEexamineFUNCTIONDisplay data at a specified address.SYNOPSISexamine [-{b,w,l,q,o,h,d}] [-{physical,virtual,gpr,fpr

The examine and deposit commands manipulate devices to get access to datawithin the system. The default device is physical memory. When another device

12.4.1 Accessing MemoryCommands are available for gaining access to memory.NoteBecause the console itself and other critical data structures reside in

An alternate method for dumping memory (or other devices or files) is the hexdump command, hd. The -l option specifies the number of bytes to display.No

>>> e r0 # Examine R0 symbolically,...gpr: 0 ( R0) 0000000000000002>>> e gpr:0 #...explicitly as device offset,...gpr: 0 ( R0) 00000

ContentsPreface ... xxi1 Product Overview1.1 Product Description ... 1–11.2 Fu

Table 1–1 Digital Alpha VME 4 Functional SpecificationsItem DescriptionAlpha AXP processor 21064A Alpha processor with on-chip 16 KB instruction and 16

12.5 Using Pipes and grep to Filter OutputTo search for specific values in a device, use a pipe with the grep command.A pipe ( | ) enables the output o

>>> ls foo # Check to see if foo exists.foo no such file>>> e 3fff000 -n 1 > foo # Redirect examine output to file foo.>>&g

>>> ps # Display complete process status.ID PCB Pri CPU Time Affinity CPU Program State-------- -------- --- -------- -------- --- ----------

To add another command to the script, use the append operator, >>. If thecommand you are appending contains characters that could be interpreted

$ create sample.show versionls -l sample(Control-Z exit)$2. Make the file compatible with the MOP load protocol. To accomplish this,run the add_header.

>>> cat sampleshow versionls -l sample>>> sampleversion V1.1-0 Jul 1 1996 10:16:59rwx- rd 512/2048 0 sampleConsole Primer 12–17

Table 12–3 Digital Alpha VME 4 Console Command SummaryCommand Options ParametersVMS like Console Commandsboot [-file filename] [-flags root,bitmap] [-hal

Table 12–3 (Cont.) Digital Alpha VME 4 Console Command SummaryCommand Options ParametersUNIX like Console Commandsrm file...set envar valuesleep timeso

Table 12–3 (Cont.) Digital Alpha VME 4 Console Command SummaryCommand Options ParametersUnique Console Commandssp process_id new_prioritystop device_p

13Console CommandsConsole mode provides the user interface that you enter when the power-onself-test (POST) completes. The console prompt is:>>&

Figure 1–1 Digital Alpha VME 4 Block DiagramMainMemoryData Path4 chipsCache andMemoryControllerCPUsysBus 128 BitsInterruptControllerFlashSuperI/

• Ctrl/S—Suspends output to the console terminal• Ctrl/Q—Resumes output to the console• Ctrl/C—Aborts the current command, if possibleThe console prog

13.1.4 Console Command DictionaryThe following commands are supported by the Digital Alpha VME 4 consoleprogram.Console Commands 13–3

allocalloc — allocate a block of memoryExports themallocroutine out to the shell so you can allocate a block of memoryfrom heap. You can then use the

allocSee Alsodynamic, freeConsole Commands 13–5

bootboot — bootstrap the systemInitializes the processor, loads a program image from the specified boot device,and transfers control to that image. If

bootA 300-byte database in the same format as the BOOTP message is used tostore the received packet. Once a BOOTP packet is broadcasted and received,t

bootThe file name defined by this environment variable becomes the file name inthe outgoing BOOTP request packet. For example:>>> set ewa0_bootp

bootEnvironmentVariable Field DescriptionEWA0_INETADDR Internet addressof the networkinterface (EWA0)Local address. TFTP and the AddressResolution Pro

bootEWA0_DEF_SINETADDREWA0_DEF_GINETADDREWA0_DEF_SUBNETMASKEWA0_DEF_INETFILEThese variables are defined in the following example:>>> set EWA0_

bootProtocol DriversYou normally use BOOTP and TFTP to bootstrap across a network. However,you can invoke the protocols as protocol drivers. The BOOTP

1.3 Physical and Environmental RequirementsThe Digital Alpha VME 4 module requires a VME chassis with sufficient cooling.You must have at least 200 lin

bootArgumentsboot_deviceA device path or list of devices from which the firmware attempts to boot, ora saved boot specification in the form of an enviro

boot4.>>> boot -fi //usr//local//bootfile//alphavme_v1_1-0-protocol bootp ewa0The system performs a TCP/IP BOOTP network boot from Ethernet p

breakbreak — break from a program loopBreaks from a for, while, or until loop. Exits the current shell with a status orreturns the status of the last

catcat — copy filesConcatenates files that you specify to the standard output. If you do not specifyfiles on the command line, the cat command copies sta

chmodchmod — change file attributesChanges the specified attributes of a file. The chmod command is a subset of theequivalent UNIX command.Syntaxchmod-+=

chmodExamples1.>>> chmod +x scriptAdds the executable attribute to the file,script.2.>>> chmod =r errlogSets the fileerrlogto read onl

chownchown — change ownership of memory blockChanges the ownership of a memory block to the specified process.Syntaxchownpid address1[address2 . . .]Ar

clearclear — delete environment variableDeletes an environment variable from the name space.NoteSome environment variables, such as BOOTDEF_DEV, are p

clear_logclear_log — clear error log in NVRAMClears and initializes the area of NVRAM used for console error logging. Theentire area of NVRAM where fa

datedate — display or change timeDisplays or modifies the current date and time. If you include no arguments, thecommand displays the current date and

Table 1–3 Typical Peak Power Supply Current and Module Power DissipationCPU Modulesw/128 MB MemoryAmps@5VAmps @ 12 V(note 1)Amps@12 VModule HeatDissip

dateExample>>> date 199208031029.00>>> date10:29:04 August 3, 1992>>>13–22 Console Commands

depositdeposit — write memory dataWrites data to a memory location, a register, a device, or a file.After initialization, if you have not specified a da

depositfpr: Floating-point register set. The data size defaults to quadword.The following symbols for address are recognized: f0, f1, . . . f31.ipr: I

deposit+ Names the location immediately following the last locationreferenced in an examine or deposit. For references to physicalor virtual memory, t

deposit-physicalThe address space is physical memory. Using this option is the same as specifyingthepmem:device.-virtualThe address space is virtual m

deposit4.>>> d -l -n 10 -s 200 pmem:0 8Deposits 8 into the first longword of each of the first 17 pages in physicalmemory.See AlsoexamineConsol

dynamicdynamic — show memoryShows the state of dynamic memory. Dynamic memory is split into two mainheaps: the console’s private heap and the remainin

dynamicExamples1.>>> dynamiczone zone used used free free utili- highaddress size blocks bytes blocks bytes zation water-------- ---------- -

echoecho — display text outputSends a line of text that you enter on the command line to the current outputdevice. The default output device is your c

echo4.>>> echo > foo ’this is the simplest way_>to create a long file. All characters will be echoed_>to file foo until the closing

evaleval — evaluate expressionEvaluates a postfix expression.Syntaxeval-ib-io-id-ix-b-o-d-xoperand1 operand2 operatorArgumentsoperand1The first numeric

eval-bDisplays the output as binary values.-oDisplays the output as octal values.-dDisplays the output as decimal values.-xDisplays the output as hexa

examineexamine — display memory dataDisplays data located at a specified address: a memory location, a register, adevice, or a file.After initialization

examinevmem: Virtual memory. All access and protection checking occur. If theaccess would not be allowed to a program running with the currentPS, the

examineipr- name Names an internal processor register. The size defaults toquadword; the address space defaults to ipr. The followingsymbols for name

examine-oThe data size is octaword.-hThe data size is hexaword.-dThe data displayed is the decoded macro instruction. Alpha instruction decode(-d) doe

examine2.>>> e-g0gpr: 0 ( R0) 0000000000000002Examine GPR register R0 by address space (-gpr option).3.>>> e gpr:0gpr: 0 ( R0) 00000

examine11.>>> examinepmem: 20040048 DB MFPR S^#2B,B^48(R1)Look at the next instruction.See AlsodepositConsole Commands 13–39

exerexer — exercise devicesExercises one or more devices by performing read, write, and compare operations.Optionally, reports performance statistics.

exer-ebend_blockSpecifies the ending block number (hexadecimal) within the file stream. Thedefault is 0.-ppass_countSpecifies the number of passes to run

2Installation ProceduresThis chapter describes how to unpack, configure, install, and verify properoperation of the Digital Alpha VME 4 module.2.1 Unpa

exern Write without lock from buffer1N Write without lock from buffer2c Compare buffer1 with buffer2- Seek to file offset prior to last read or write?

exerDescriptionExercises one or more devices. As described in the preceding overview section,the exer command uses two buffers, buffer1 and buffer2. T

exerYou can use a random number generator to seek to varying device locationsbefore performing either a read or write operation. Randomization is achi

exerThe exer command returns an error code immediately after a read, write, orcompare error, if the D_HARDERR environment variable is set to HALT. Whe

exer5.>>> exer -eb 64 -bc 4 -a ’?w-Rc’ dka0A destructive write test over block numbers 0 through 100 on diskdka0. Thepacket size is 2048 byte

exer7.>>> set myd 0>>> exer -bs 1 -bc a -l a -a ’w’ -d1 ’myd myd ~ =’ foo>>> clear myd>>> hd foo -l a00000000 ff 0

exerSee Alsomemexer13–48 Console Commands

exitexit — exit current shellExits the current shell with the specified status or returns the status of the lastcommand executed.Syntaxexitexit_valueAr

falsefalse — return failure statusReturns a failure status.SyntaxfalseExample>>> while false ; do echo foo; done>>>13–50 Console Com

freefree — deallocate memoryFrees a block of memory that has been allocated from a heap. The block isreturned to the appropriate heap.Syntaxfreeaddres

Figure 2–1 Digital Alpha VME 4 Module ComponentsMLO-0132401234567Optional PMC I/O companion cardI/O moduleDigital Alpha VME 4 moduleMemory modulesCach

grepgrep — search for regular expressionsGlobally searches for regular expressions and prints any lines containingoccurrences of the regular expressio

grep+ Repeated matching.When placed after a pattern, the plus sign indicates that the patternshould match one or more times. For example, [0-9]+ match

grep2.>>> alloc 2000FFFFE0>>> deposit -q pmem:fffff0 0>>> e -n 3 ffffe0pmem: FFFFE0 EFEFEFEFEFEFEFEFpmem: FFFFE8 EFEFEFEFEF

hdhd — dump file contentsDumps the contents of a file in hexadecimal and ASCII format.Syntaxhd[-{byte | word | long | quad}] file...Argumentsfile...Specifi

hd3.>>> -word foo00000000 6874 2065 7571 6369 206B 7262 776F 206E the quick brown00000010 6F66 2078 756A 706D 6465 6F20 6576 2072 fox jumped

helphelp— help on commandsDefines and shows the syntax for each command that you specify on the commandline. If you do not specify a command, the help

help2.>>> help * # List all topics and associated text.Requests help on all topics.3.>>> help exRequests help on all commands that b

init_evinit_ev — initialize environment variablesSets all environment variables to their default values.Once you issue this command, you need to reset

initializeinitialize — initialize the console, a device, or theprocessorInitializes the console, a device, or the processor.Syntaxinit[ialize] [-c] [-

killkill — delete processDeletes the processes listed on the command line. Processes are killed by makinga call to a kernel function with the process

Table 2–1 Digital Alpha VME 4 Hardware Kit ItemsItem Part NumberDigital Alpha VME 4/224 KitDigital Alpha VME 4 module I/O assembly 70–32976–04 (includ

lineline — read a lineCopies one line (up to a new line) from the standard input channel of the currentprocess to the standard output channel of the c

lsls — list filesLists files or inodes in the system. Inodes are RAM disk files, open channels, andsome drivers. RAM disk files include script files, diagn

memexermemexer — memory exerciserStarts a specified number of graycode memory test processes running in thebackground. Each test randomly allocates and

memtestmemtest — memory testTests memory with any or all of four tests:Test DescriptionGraycode memory test Writes, reads, and verifies a graycode patt

memtest2. Reads each location, verifies the data, and writes the inverse of the data. Theread-verify-write is done one longword at a time. This causes

memtestThe random test:1. Obtains an address index into the Linear Congruential Generator (LCG)structure that is dependent on the specified length. The

memtestIf you issue a Ctrl/C or the kill command with a PID in the middle of testing,thememtestprocess might not abort right away. To increase speed o

memtest-rsrandom_seedSpecifies the random seed. Use this option only with the -rb option. The defaultis 0.-rbSpecifies to randomly allocate and test all

memtest-gSpecifies a group name. Currently, the only group supported is MFG.-seSpecifies a soft error threshold.Examples1.>>> memtest -sa 20000

memtestSee AlsomemexerConsole Commands 13–71

Table 2–2 Digital Alpha VME 4 Memory ModulesMemory Size(MB) Kit Number Part Number16 EBMXM-DB 54–24659–AB32 EBMXM-EB 54–24659–AA64 EBMXM-FB 54–24645–A

netnet — MOP functionUsing a specified port, performs basic maintenance operations protocol (MOP)operations.The net command performs basic MOP operatio

net-l0Sends an Ethernet loopback to a specified destination node. You specify theaddress of the destination node with the -da option.-l1Requests a MOP

net-lwwait_in_secsWaits the specified number of seconds for the loop messages from the -l1 optionto return. If the messages do not return in the specifi

psps — show processDisplays the system state in the form of process status and statistics.SyntaxpsExample>>> psCPUID PCB Pri Time Affinity CP

pwruppwrup — run power-on diagnosticsRuns the power-on diagnostics script. The pwrup command initializes networkenvironment variables and runs memory

rmrm — remove fileRemoves the specified files from the file system. Allocated memory is returned tothe heap.Syntaxrmfile1[file2 . . .]Argumentsfile1 file2 . .

sasa — set process affinityChanges the affinity mask of a process. The affinity mask of a process specifiesthe processors on which the process can run.Syn

semaphoresemaphore — show system semaphoresShows all the semaphores known to the system by traversing the semaphorequeue.SyntaxsemaphoreExample>>

setset — set environment variableSets or modifies the value of an environment variable. Some of the environmentvariables are stored in nonvolatile memo

setthe factory to the device that contains the factory-installed software. For systemsthat do not ship with factory-installed software, the default se

Table 2–4 Additional Hardware Installation ItemsItem Supplier Part NumberSerial line cable for console and auxiliaryterminalsDigital BC16E– nn1IEEE 80

set5.>>> set AUTO_ACTION BOOTSets the system’s default console action to boot after an error, halt, orpower-on.6.>>> set BOOT_FILE a

set ledset led — display char on LEDDisplays a character on the front panel light emitting diode (LED).Syntaxset ledchar[-b]ArgumentscharSpecifies the

set reboot sromset reboot srom — set reboot mode to Serial ROMMini-ConsoleEnters the Serial ROM (SROM) Mini-Console.The only valid (and necessary) arg

set toy sleepset toy sleep — disable TOY clock’s internal oscillatorDisables the DS1386 TOY clock’s internal oscillator, lengthening the shelf lifeof

shsh — create new shellCreates another shell process. Each shell process implements most of thefunctionality of the Bourne shell.Syntaxsh-x-v-d[-l] [-

shExample>>> sh # start a new shell>>> # the new shell’s prompt>>> sh -v <foo # execute command file "foo" and

showshow — display system informationDisplays the current value of an environment variable or other system parameter.Syntaxshow [{config, device, hwrpb

showCommonly Used Environment Variablesauto_actionDisplays the console action following an error halt or power on. The action can behalt, boot, or res

show configshow config — display system configurationDisplays the system configuration.Syntaxshow configExample>>> show configDigital Equipment Co

show deviceshow device — displays devicesDisplays the devices and controllers in the system. By default, all devices andcontrollers that respond are s

3 Operating the Digital Alpha VME 4 Computer3.1 Controls and Indicators ... 3–13.2 Console Mode ...

2.2 InstallationTo install the Digital Alpha VME 4 module, perform the following steps:1. Select two adjacent slots in your VME backplane for the Digi

show device2.>>> show device eewa0.0.0.6.0 EWA0 08-00-2B-1D-27-AADisplays devices that start with ‘‘e’’.3.>>> show device *k* # Show

show hwrpbshow hwrpb — display HWRPBDisplays the address of the Alpha hardware restart parameter block (HWRPB).Syntaxshow hwrpbExample>>> sho

show ledshow led — display LED characterDisplays the current character being displayed on the front LED panel.Syntaxshow led [-hex]Options-hexDisplays

show mapshow map — display memory mapDisplays the current system virtual memory map.NoteThe map is empty after all console initialization. To fill in t

show_logshow_log — display NVRAM error log informationDisplays console-detected fault information that was previously stored in theerror log area of N

show_log2.>>> show_log -n 3=============================== F A U L T #1 ================================Time of Error: 13:10:06 9-AUG-1994Mac

sleepsleep — suspend executionSuspends execution of a console process for a specified number of seconds. Theconsole process temporarily wakes up every

sortsort — sort a fileArranges the lines of a file in lexicographic order and writes the results toSTDOUT. The size of the file that sort can handle is l

spsp — set priorityModifies the priority of a process. Changing the priority of the process impactsthe behavior of the process and the rest of the syst

startstart — start programStarts program execution at the specified address or starts drivers.Syntaxstart [-drivers [device_prefix]] [address]Argumentsa

Figure 2–2 Digital Alpha VME 4 Module LayoutMLO-013237DCBADCBA512 KB 2 MB123CBA45678512 KB2 MBCBA9Cache memory connectorsMemory connectorsCache configu

stopstop — stop CPU or deviceStops the CPU or a specified device.Syntaxstop [-drivers [device_prefix]] [processor_num]Argumentsprocessor_numSpecifies the

updateupdate — update flash ROMs on the systemLoads new firmware into the flash ROMs (FEPROMs). To modify the flash ROMs,you must close DIP switch #2 on t

update-targetdeviceSpecifies the device that contains the FEPROMs to be upgraded. Valid targetsare CONSOLE and USERFLASH.Examples1.>>> update

updateThe program will take at most several minutes.Erasing the target flash device...Erasure completed.Programming...Programming comp

AModule Connector PinoutsSections A.1 through Section A.5 provide pinout information for the Alpha VME4:• CPU connector• I/O Type 1 card connector• Pr

A.2.1 VMEbus (J1) Connector PinoutsTable A–1 lists the pinouts for the VMEbus (J1) connector (P2).Table A–1 VMEbus (J1) ConnectorPin Row A Row B Row C

Table A–1 (Cont.) VMEbus (J1) ConnectorPin Row A Row B Row C27 VCC VME_D28 PP_PE28 Ground VME_D29 PP_BUSY29 Ground VME_D30 PP_ACK_L30 Ground VME_D31 P

A.2.3 Ethernet (J9) Connector PinoutsTable A–3 lists the pinouts for the Ethernet (J9) connector. Figure A–2 shows apinout diagram.Table A–3 Ethernet

Table A–4 (Cont.) Primary Breakout Module Connector PinoutsPin Row A Row B Row C5 SCSI_DATA4_L N/C KBCLK6 SCSI_DATA5_L N/C WD_STATUS_OC7 SCSI_DATA6_L

Figure 2–3 I/O Module LayoutMLO-01323821345 6789ONOFFOPEN432110Console serial portAuxiliary serial portReset/halt switchTwisted pair Ethernet connecto

Figure A–3 Primary Breakout Module Connector PinoutsSide 1J2 (SCSI)XP2J1125049C1B1A1C32B32A32Side 2C32B32A32C1B1A1C32B32A32C1B1A1J3J4MLO-013551A.4 Sec

Figure A–4 Secondary Breakout Module Connector PinoutsJ6J2J52613A32C32A1C1C32B32A32C1B1A1MLO-013552P214143214321J4J1Sections A.4.1 and A.4.2 provide m

Table A–5 Keyboard and Mouse (J1) ConnectorPin Signal1 MOUSE_DATA2 KBRD_DATA3 Ground4 VCC5 MOUSE_CLOCK6 KBRD_CLOCKFigure A–5 Keyboard and Mouse (J1) P

Table A–6 (Cont.) Parallel Port (J6) Connector9 PP_DATA710 PP_ACK_L11 PP_BUSY12 PP_PE13 PP_SLCT14 PP_AFD_L15 PP_ERR_L16 PP_INIT_L17 PP_SLIN_L18-25 Gro

Table A–7 PMC I/O Companion Card Mouse (J2) ConnectorPin Signal1 MOUSE_DATA2 KBRD_DATA3 Ground4 VCC5 MOUSE_CLOCK6 KBRD_CLOCKTable A–8 PMC I/O Companio

IndexAACFAIL* assertion, 11–8Address mapping, 5–1Address modifier, 10–6Address spacecacheable, 5–4DECchip 21071-CA CSR, 5–4DECchip 21071-DA, 7–7DECchip

BOOTED_FILE environment variable,3–4BOOTED_OSFLAGS environmentvariable, 3–4BOOTP, 13–6BOOT_DEV environment variable, 3–4BOOT_FILE environment variable

Commands (cont’d)exit, 13–49false, 13–50free, 13–51grep, 13–52hbeat_diag, 4–9hd, 13–55help, 13–57i8254_diagwith -t 1, 4–10with -t 2, 4–11with -t 3, 4–

Connector pinouts (cont’d)I/O Type 1 card, A–1keyboard and mouse, A–7parallel port, A–8PMC I/O companion card, A–9primary breakout module, A–4secondar

DECchip 21040-AA, 8–3See also Ethernet controllerDECchip 21071-BA, 6–1block diagram of, 6–30DECchip 21071-CA, 6–1block diagram, 6–2CSR address space,

2. Set the configuration switches on the I/O module as outlined in Table 2–5,Table 2–6, and Table 2–7. Also refer to Figure 2–3 for the configurationswi

Diagnostics (cont’d)NCR810 internal loopback test, 4–25NCR810 interrupt test, 4–26NCR810 PCI configuration registertest, 4–24NVRAM address-on-address t

D_OPER environment variable, 3–5D_PASSES environment variable, 3–5D_REPORT environment variable, 3–5D_SOFTERR environment variable, 3–5D_STARTUP envir

GGeneral control register, 6–11Global switches, 10–14Global timing register, 6–27grep command, 13–52using pipe with, 12–12HHalt switch, 3–2Hardware re

Interval timing registers, 9–25ioclrlock command, 7–6iogrant signal, 7–6ISAbus controller recovery timer register,9–4clock divisor register, 9–4JJumpe

memtest command, 13–65Merge buffer, memory, 6–31MODE environment variable, 3–6dependence of diagnostic tests on, 4–7Modesblock data transfer, 10–7cont

OOperating system, booting, 3–7> operator, 12–12Operatorsredirection operator, 12–12shell, 12–3Order numbers, 2–35PPage monitor CSR, 10–13PALdevice

PCI mezzanine card adapter, 8–11PCI-to-physical memory addressing, 5–15PD bits, 9–10Performance, 1–2Physical addresses, decoding of by PCIhost bridge,

Registers (cont’d)dummy registers, 7–15error and diagnostic status register,6–13error high address register, 6–19error low address register, 6–18exami

RegistersVIC (cont’d)local interrupt vector base register,11–7register, testing, 4–28release control register, 10–20VIP PCI configuration registertesti

show led command, 13–94show map command, 13–95show_log command, 13–96Signal, iogrant, 7–6Single mode data transfers, 10–7SIO chipSee Super I/O chipsle

Table 2–7 Supported Switch Settings for Digital Alpha VME 4 Modules in OtherThan Slot 1 (Nonsystem Controller)Switch Setting1 Closed2 Open3 Closed14 O

Timers (cont’d)VMEbus arbitration, 10–21VMEbus timeout, 10–21VMEbus transfer, 10–223 timers loopback test, 4–11Timing register A, 6–25Timing register

VME interface (cont’d)registers, summary of, 10–37restrictions, 10–40scatter-gather entry, outbound, 10–4scatter-gather mapping, outbound,10–4single m

Figure 2–4 Installing the Main Memory ModulesMLO-0132463124Memory bank 0 slots A and BMemory bank 1 slots A and BOrientation notchesMemory connectorTa

Table 2–8 Digital Alpha VME 4 Memory ConfigurationsMemory Size(MB)Bank 0Slot ABank 0Slot BBank 1Slot ABank 1Slot B16 8 832888832 16 1648 8 8 16 1664 16

Figure 2–5 Cache Memory Modules1MLO-0132452Orientation notchCache memory connector5. The J9 and J10 jumpers are preconfigured for your Digital Alpha VM

Table 2–10 J10 Cache Jumper SettingsA B C Total Size SpeedIn In In Disable cacheIn In Out ReservedIn Out In 2 MB 12 nsIn Out Out ReservedOut In In 512

Figure 2–6 Installing the Digital Alpha VME 4 ModuleMLO-0132361CautionYou must install the primary breakout module (54-24663-01) includedin your hardw

5 System Address Mapping5.1 CPU Address Mapping to PCI Space . . ... 5–15.1.1 Cacheable Memory Space (0x000000000 to0x0FFFFFFFF) ...

Figure 2–7 Alpha VME 4 Primary Breakout Module135246MLO-013263!Part Number: 54-24663-01Part Number: 54-22605-017. Set the SCSI termination jumper on t

component. The monitoring device must also be connected to the sameground reference as the Digital Alpha VME 4 module.The external watchdog reset sign

Figure 2–9 Connecting the SCSI Cable to the Primary Breakout ModuleMLO-01324110. Install the primary breakout module (refer to Figure 2–10). Ensure th

Figure 2–10 Installing the Primary Breakout ModuleMLO-01326411. A secondary breakout module is included in the hardware kit, which you canconnect to t

Figure 2–11 Secondary Breakout Module JumpersMLO-0133533 14 2Keyboard / MouseEnabled3 14 23 14 2Keyboard / MouseDisabled3 14 23124Mous

Figure 2–12 Connecting the Secondary Breakout Module to the PrimaryBreakout ModuleMLO-0132661 2Primary breakout module (54-24663-01)Secondary breakout

Figure 2–13 Connecting Network and Console Terminal CablesMLO-0133521 2 3NetworkConsoleAuxiliary16. Insert blank panels into the vacant slots of the V

2.2.1 Installing the PMC I/O Companion CardFigure 2–14 shows the layout of the PMC I/O companion card.NoteTo install the PMC I/O companion card with t

Signaling level jumper (jumper MUST be set to 5.0 V)PMC option slotsVME connectorsI/O-to-P2 signal connectorCautionPerform the following steps gently

seating the Alpha VME module in the VME chassis. If you do not retractthe screws completely:• The Alpha VME module might not seat properly.• The press

6.5 Address Space of Control/Status Registers ... 6–86.6 Description of CSRs ... 6–116.6.1 General Control Regist

Figure 2–15 Connecting the PMC I/O Companion CardMLO-0132652–26 Installation Procedures

Figure 2–16 Installing the PMC I/O Companion CardMLO-01341119. Return to step 6 in Section 2.2 for instructions on installing the DigitalAlpha VME 4 m

Table 2–11 SROM Test Numbers and DescriptionsLED Display COM1 Meaning8 - Nbus bus has been reset and SIO configured.7 7.. COM1 port has been initialize

Table 2–12 Console Code Test Letters and NamesTest Letter Test NameA SCSI control and status register (CSR) testB Heartbeat timer testC Interval timer

If all SROM and flash ROM-based diagnostics pass, and an auto_action1bootcommand has been set, the>>>console prompt appears on the console ter

Table 2–13 TroubleshootingSymptom Corrective ActionNo LEDs lit, no console prompts. Check power. If 5 V power is out ofspecification, the module will b

2.5 Repair and Warranty Information2.5.1 Return to Digital Hardware MaintenanceThe following products come with a 1 year Return to Digital warranty as

2.5.2.2 Return-to-Digital ProcessTo return products under warranty, contact the Digital Customer Support Centerin your particular geography. The Custo

• Assume all risk of loss or damage to field replaceable units in transit toDigital.2.5.2.6 Pre-Call ChecklistTo allow Digital to assist you quickly an

2.5.4 Field Replaceable Units and Order NumbersTable 2–15 lists the available field replacable units and their associated ordernumbers.Table 2–15 Field

7.3.8 PCI Master Timeout . . . ... 7–77.3.9 Address Stepping in Configuration Cycles ... 7–77.4 Address Space of Control/Sta

3Operating the Digital Alpha VME 4Computer3.1 Controls and IndicatorsFigure 3–1 shows the front panel controls and indicators of the Digital AlphaVME

Figure 3–1 Controls and Indicators12 3 4MLO-013262Table 3–1 Controls and IndicatorsControl or Indicator DescriptionReset/Halt switch A switch that res

3.2 Console ModeSections 3.2.1 and 3.2.2 explain how a Digital Alpha VME 4 system enters andexits console mode.3.2.1 Entering Console ModeA Digital Al

NoteDo not change the settings of the environment variables withoutunderstanding the implications of the changes.Table 3–2 lists the environment varia

Table 3–2 (Cont.) Environment Variable SummaryVariable DescriptionD_EOP Specifies whether end-of-pass messages are to be displayed.D_GROUP Specifies the

Table 3–2 (Cont.) Environment Variable SummaryVariable DescriptionEWA0_DEF_SINETADDR Specifies the initial value for EWA0_SINETADDR whenthe interface’s

Table 3–2 (Cont.) Environment Variable SummaryVariable DescriptionVME_A32_BASE Specifies the base address of VMEbus A32 space.VME_A32_SIZE Specifies the

4Diagnostics4.1 OverviewThis chapter describes the Digital Alpha VME 4 power-on self-test (POST)diagnostics and additional ROM-based diagnostics (RBDs

9.2.1 Module Display Control Register . ... 9–59.2.2 Module Configuration Register... 9–69.2.3 Interrupt and Interrupt Mask

Failures detected by the SROM-based tests are indicated by the test sequencehalting and the LED display permanently showing the failing test number.A

Table 4–1 Console Diagnostic TestsHW Under Test CommandMemory and Cache- Memory exerciser test memtest or mem_exNetwork Interface- DECchip 21040 netwo

Table 4–1 (Cont.) Console Diagnostic TestsHW Under Test Command- SCSI device exer exer dkTimers- Heartbeat timer test hbeat_diag -t 1- Interval timer

LED DisplayOutput onConsole Meaning8 – Nbus bus has been reset and system I/O (SIO) configured.7 7.. COM1 port has been initialized (9600 baud).6 6.. B

POST Non-Volatile RAM DiagnosticPOST Non-Volatile RAM DiagnosticThe POST Non-Volatile RAM (NVRAM) diagnostic test verifies the module’sNVRAM. It perfor

POST Memory DiagnosticPOST Memory DiagnosticThe POST memory diagnostic test verifies system memory. It runs with ECCenabled. If the test detects a memo

4.3.4 Console Diagnostic Test DescriptionsThis section provides details on the tests, which are available to the console, thatyou might run during sys

Heartbeat Timer TestHeartbeat Timer TestThe heartbeat timer diagnostic test verifies that a heartbeat interrupt isgenerated at the correct interval (10

Interval Timer TestsInterval Timer TestsThe interval timer tests test the functionality of the 8254 interval timer chip andsurrounding external circui

Interval Timer Tests• See the Intel 8254 interval timer sheet for more details.Timer 2 Square Wave TestThis test exercises timer 2. In the Digital Alp

10.2.3 Interprocessor Communication ... 10–1410.2.3.1 Interprocessor Communication Registers . . ... 10–1410.2.3.2 Interprocessor C

Interval Timer TestsThis test essentially emulates the realtime time provider and slave scheme foundin the Realtime Clock and Interval Device Driver f

Interval Timer TestsThis test enables only timer 0 as done in test 3 but does not use timer 1 ortimer 2. The clock and gate come from the timers on th

Interval Timer Tests• Due to hardware limitations on interrupt detection, the value programmedinto timer 2 must be greater than 2.• See the Intel 8254

Interval Timer TestsFigure 4–1 Loopback Descriptions for Interval Timer Test 3 and 4ML013463Configuration for Interval Timer test 3To make a loopbac

DECchip 21040 Ethernet Controller TestsDECchip 21040 Ethernet Controller TestsThese diagnostics verify that the internal and external loopback mechani

DECchip 21040 Ethernet Controller TestsDECchip 21040 PCI Configuration Register DumpThis test reads the PCI configuration registers of the DECchip 21040

DALLAS DS1386 RAMified Watchdog Timekeeper TestsDALLAS DS1386 RAMified Watchdog Timekeeper TestsThe DS1386 consists of 32 KB of NVRAM and a realtime clo

DALLAS DS1386 RAMified Watchdog Timekeeper TestsNVRAM Address-On-Address TestThe NVRAM locations in the DS1386 are byte wide. Therefore, you do nothave

DALLAS DS1386 RAMified Watchdog Timekeeper TestsConsole Command: ds1386_diag -t 3Command Options:• -dd: print detailed test information on each pass.•

DALLAS DS1386 RAMified Watchdog Timekeeper TestsConsole Command: ds1386_diag -t 4Command Option:-dd: print detailed test information on each pass.Misce