Digital Equipment Corporation Digital Semiconductor 21140A User Manual

Digital Equipment CorporationMaynard, Massachusettshttp://www.digital.com/semiconductorDIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller D

2 21140A Overview Features1.2 FeaturesThe 21140A has the following features:• Offers a single-chip Fast Ethernet controller for PCI local bus: - Prov

21140A Overview 3 Microarchitecture• Supports PCI read multiple command• Supports early interrupts on transmit and receive for improved performance• I

4 21140A Overview Microarchitecture• RxM—Handles all CSMA/CD receive operations, and transfers the data from the ENDEC to the receive FIFO.• Physical

21140A Overview 5 MicroarchitectureFigure 1 21140A Block DiagramRxFIFO321641411610 Mb/sSerial InterfacePhysical CodingSublayerMII/SYM InterfaceScramb

6 Pinout 2 PinoutThe 21140A is packaged in a 144-pin plastic quad flat pack (PQFP). The tables in this section provide a description of the pins and

Pinout 7 Figure 2 21140A Pinout Diagram (Top View)LJ-04479.AI4vssvddmii_mdcmii_mdioncbr_a<1>br_a<0>br_ce_lbr_ad<7>vddbr_ad<6>v

8 Pinout Signal Reference Tables2.1 Signal Reference TablesTable 2 provides an alphabetical list of the 21140A logic names and their pin numbers. Tab

Pinout 9 Signal Reference Tables ad<23> 24 devsel_l 42 mii/sym_rxd<2> 117mii/sym_rxd<3> 118 req_l 8 srl_tclk 139mii/sym_tclk 123 rst

10 Pinout Signal Reference TablesTable 4 provides a functional description of each of the 21140A signals. These signals are listed alphabetically. T

Pinout 11 Signal Reference Tablesbr_a<1> O 103 Boot ROM address line bit 1. This pin also latches the boot ROM address and control lines by t

12 Pinout Signal Reference Tablesframe_l I/O 39 The frame_l signal is driven by the 21140A (bus master) to indicate the beginning and duration of an

Pinout 13 Signal Reference Tablesirdy_l I/O 40 Initiator ready indicates the bus master’s ability to complete the current data phase of the transactio

14 Pinout Signal Reference Tablesmii_mdio I/O 105 MII management data input/output transfers control information and status between the PHY and the 21

Pinout 15 Signal Reference Tablespci_clk I 5 The clock provides the timing for the 21140A related PCI bus transactions. All the bus signals are sampl

16 Pinout Signal Reference Tablesserr_l O/D 46 If an address parity error is detected and CFCS bit 8 (serr_l enable) is enabled, the 21140A asserts bo

Pinout 17 Signal Reference Tablessrl_tclk I 139 Transmit clock carries the transmit clock supplied by an external ENDEC. This clock must always be ac

18 Pinout Pin Tables2.2 Pin TablesThis section contains four types of pin tables:• Table 5 lists the input pins.• Table 6 lists the output pins.• Tabl

Pinout 19 Pin Tables Table 5 Input PinsSignal Active Level Signal Active Levelgnt_l Low sd Highidsel High sr_do —mii_clsn High srl_clsn

20 Pinout Signal Grouping by Function 2.3 Signal Grouping by Function Table 9 lists the signals according to their interface function. devsel

Pinout 21 Signal Grouping by Function Transmit enable mii_txenCollision detect mii_clsnError reporting mii_err Data control mii_dv, mii_crs MI

Important NoticeAs of May 17, 1998, Digital Equipment Corporation’s StrongARM, PCI Bridge, and Networking component businesses, along with the chip f

22 Electrical and Environmental Specifications Voltage Limit Ratings3 Electrical and Environmental SpecificationsThis section contains the electrical

Electrical and Environmental Specifications 23 Supply Current and Power Dissipation3.3 Supply Current and Power DissipationThe values in Table 12 are

24 Electrical and Environmental Specifications PCI Electrical Parameters3.4.2 PCI ResetPCI reset (pci_rst) is an asynchronous signal that must be acti

Electrical and Environmental Specifications 25 PCI Electrical Parameters3.4.3 PCI Clock SpecificationsThe clock frequency range for the PCI is between

26 Electrical and Environmental Specifications PCI Electrical Parameters3.4.4 Other PCI SignalsFigure 5 shows the timing diagram characteristics, and

Electrical and Environmental Specifications 27 Serial, MII/SYM, Boot ROM, Serial ROM, and General-Purpose Port Interface 3.5 Serial, MII/SYM, Boot R

28 Electrical and Environmental Specifications Serial Network Port Timing3.6 Serial Network Port Timing This section describes the serial network port

Electrical and Environmental Specifications 29 Serial Network Port Timing3.6.2 Serial 10-Mb/s Timing—CollisionFigure 7 shows the serial network port c

30 Electrical and Environmental Specifications Serial Network Port Timing3.6.3 Serial 10 Mb/s Timing—Receive, Start of PacketFigure 8 shows the serial

Electrical and Environmental Specifications 31 Serial Network Port Timing3.6.4 Serial 10-Mb/s Timing—Receive, Start, and End of PacketFigure 9 shows t

December 1997While DIGITAL believes the information included in this publication is correct as of the date of publication, it is subject to change wit

32 Electrical and Environmental Specifications MII/SYM Port Timing3.7 MII/SYM Port TimingThis section describes the MII/SYM port timing limits.3.7.1 M

Electrical and Environmental Specifications 33 MII/SYM Port Timing 1±50 parts per million.2t = 1 for 100-Mb/s operation and t = 10 for 10-Mb/s operati

34 Electrical and Environmental Specifications MII/SYM Port Timing3.7.2 MII/SYM 10/100-Mb/s Timing—ReceiveFigure 11 shows the MII/SYM port receive tim

Electrical and Environmental Specifications 35 MII/SYM Port Timing3.7.3 MII/SYM 10/100-Mb/s Timing—Signal DetectFigure 12 shows the MII/SYM port signa

36 Electrical and Environmental Specifications MII/SYM Port Timing3.7.4 MII/SYM 10/100-Mb/s Timing—Receive ErrorFigure 13 shows the MII/SYM port recei

Electrical and Environmental Specifications 37 Boot ROM Port Timing3.8 Boot ROM Port TimingThis section describes the boot ROM port timing.3.8.1 Boot

38 Electrical and Environmental Specifications Boot ROM Port Timing3.8.2 Boot ROM Write TimingFigure 16 shows the boot ROM write timing characteristic

Electrical and Environmental Specifications 39 Serial ROM Port Timing3.9 Serial ROM Port TimingFigure 17 shows the serial ROM port timing, and Table 2

40 Electrical and Environmental Specifications External Register Timing3.10 External Register TimingFigure 18 shows the external register read timing

Electrical and Environmental Specifications 41 Joint Test Action Group—Test Access Port3.11 Joint Test Action Group—Test Access PortThis section provi

iii Contents1 21140A Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 General Description .

42 Electrical and Environmental Specifications Joint Test Action Group—Test Access PortFigure 20 JTAG Boundary-Scan Timing Diagram1Parameter design gu

Mechanical Specifications 43 4 Mechanical SpecificationsThe 21140A is contained in an industry standard 144-pin PQFP. Table 33 lists the mechanical s

44 Mechanical Specifications Figure 21 144-PIN PQFP Package LJ04510B .AI4A// 0.13 CC- C -Datum PlaneSeating Planeccc- H -- Basic Dimension- Reference

Support, Products, and Documentation 45 A Support, Products, and DocumentationTo view current product update and errata revision information, please v

46 Support, Products, and Documentation DIGITAL Semiconductor ProductsTo order the DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller and E

Support, Products, and Documentation 47 DIGITAL Semiconductor DocumentationThe following table lists some of the available DIGITAL Semiconductor docum

iv 4 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43A Support, Products, and Documentation . .

v Figures1 21140A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 21140A Pinout Diagram (To

vi Tables1 Index to Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Logic Signals. . . . .

21140A Overview 1 1 21140A OverviewThe DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller (21140A) supports the peripheral component interc