Digital Equipment Corporation Digital Semiconductor 21140A User Manual

Digital Equipment CorporationMaynard, Massachusettshttp://www.digital.com/semiconductor DIGITAL Semiconductor 21140APCI Fast Ethernet LAN ControllerH

viii Examples4–1 Perfect Filtering Buffer ...4–234–2 Imperfect

4–12 Host Communication Descriptor Lists and Data Buffers4.2.2 Transmit DescriptorsFigure 4–7 shows the Transmit descriptor format.Note: Descriptor ad

Host Communication 4–13 Descriptor Lists and Data Buffers4.2.2.1 Transmit Descriptor 0 (TDES0)TDES0 contains transmitted frame status and descriptor o

4–14 Host Communication Descriptor Lists and Data BuffersTable 4–6 TDES0 Transmit Descriptor 0 Description(Sheet 1 of 2)Field Description31 OWN—Own Bi

Host Communication 4–15 Descriptor Lists and Data Buffers9 LC—Late CollisionWhen set, indicates that the frame transmission was aborted due to collisi

4–16 Host Communication Descriptor Lists and Data Buffers4.2.2.2 Transmit Descriptor 1 (TDES1)Figure 4–9 shows the TDES1 bit fields and Table 4–7 desc

Host Communication 4–17 Descriptor Lists and Data Buffers27 SET—Setup PacketWhen set, indicates that the current descriptor is a setup frame descripto

4–18 Host Communication Descriptor Lists and Data BuffersTable 4–8 lists the filtering types and Table 3–45 provides additional information on filteri

Host Communication 4–19 Descriptor Lists and Data BuffersFigure 4–10 TDES2 Transmit Descriptor 2 4.2.2.4 Transmit Descriptor 3 (TDES3) Figure 4–11 sho

4–20 Host Communication Descriptor Lists and Data BuffersList of table abbreviationsLO—Loss of carrier (TDES0<11>) NC—No carrier (TDES0<10>

Host Communication 4–21 Descriptor Lists and Data Buffers4.2.3.1 First Setup FrameA setup frame must be processed before the reception process is star

ix Figures1–1 21140A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–52–1 21140A Pinout Diag

4–22 Host Communication Descriptor Lists and Data BuffersFigure 4–12 shows the perfect filtering setup frame buffer format of the addresses.Figure 4–1

Host Communication 4–23 Descriptor Lists and Data BuffersExample 4–1 shows a perfect filtering setup buffer (fragment).Example 4–1 Perfect Filtering B

4–24 Host Communication Descriptor Lists and Data Buffers4.2.3.4 Imperfect Filtering Setup Frame BufferThis section describes how the 21140A interpret

Host Communication 4–25 Descriptor Lists and Data BuffersFigure 4–14 Imperfect Filtering Setup Frame FormatBits are sequentially numbered from right t

4–26 Host Communication Descriptor Lists and Data BuffersExample 4–2 shows an imperfect filtering setup frame buffer.Example 4–2 Imperfect Filtering

Host Communication 4–27 Descriptor Lists and Data BuffersExample 4–2 (Cont.) Imperfect Filtering Buffer xxxx1000 xxxx0000 xxxx0000 xxx

4–28 Host Communication Descriptor Lists and Data Buffers Example 4–2 (Cont.) Imperfect Filtering Buffer xxxxxxxxSetup frame buffer while in big e

Host Communication 4–29 Descriptor Lists and Data Buffers Example 4–2 (Cont.) Imperfect Filtering Buffer 0000xxxx 0000xxxx 4000xxx

4–30 Host Communication Functional Description Displays the first part of an imperfect filter setup frame buffer, in big endian byte ordering, with se

Host Communication 4–31 Functional DescriptionAfter either a hardware or software reset command, the first bus transaction to the 21140A should not be

x 5–5 Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–85–6 Memory Write . . . . . .

4–32 Host Communication Functional Description In addition to the arbitration scheme listed in Table 4–12, two other factors must be considered:• The

Host Communication 4–33 Functional Description4.3.3 InterruptsInterrupts can be generated as a result of various events. CSR5 contains all the status

4–34 Host Communication Functional Description4.3.4 Startup ProcedureThe following sequence of checks and commands must be performed by the driver to

Host Communication 4–35 Functional Description4.3.5 Receive ProcessWhile in the running state, the receive process polls the receive descriptor list,

4–36 Host Communication Functional Descriptionbit is reset to 0 either as the data buffers fill up or as the last segment of a frame is transferred to

Host Communication 4–37 Functional Description4.3.6 Transmit ProcessWhile in the running state, the transmit process polls the transmit descriptor lis

4–38 Host Communication Functional DescriptionAs the transmit process starts execution, the first descriptor must have TDES1<29> set. When this

Host Communication 4–39 Functional Description4.3.6.3 Transmit Process State TransitionsTable 4–14 lists the transmit process state transitions and th

4–40 Host Communication Functional DescriptionRunning Parity error detected by memory or host bus. Running Transmission is cut off and fatal bus error

Host Bus Operation 5–1 5Host Bus OperationThis chapter describes the commands and operations of read and write cycles for a bus slave and a bus master

xi Tables2–1 Functional Description of 21140A Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43–1 Configuration Registers Mapp

5–2 Host Bus Operation Bus Commands5.2 Bus CommandsTable 5–1 lists the bus commands.1Initiator support for this command is controlled by CSR0<21>

Host Bus Operation 5–3 Bus Slave Operation• Configuration read• Configuration write• Memory read• Memory write• Memory read/write (includes memory wri

5–4 Host Bus Operation Bus Slave OperationFigure 5–1 Slave Read Cycle5.3.2 Slave Write Cycle (I/O or Memory Target)Figure 5–2 shows a typical slave wr

Host Bus Operation 5–5 Bus Slave OperationFigure 5–2 Slave Write Cycle5.3.3 Configuration Read and Write CyclesThe 21140A provides a way for software

5–6 Host Bus Operation Bus Master OperationFigure 5–3 Configuration Read Cycle5.4 Bus Master OperationAll memory accesses are completed with the 21140

Host Bus Operation 5–7 Bus Master Operation3. The 21140A ensures that its gnt_l is asserted on the clock edge that it wants to drive frame_l. (If gnt

5–8 Host Bus Operation Bus Master Operation5. The memory controller drives the data on the ad lines and asserts trdy_l.6. The 21140A samples the data

Host Bus Operation 5–9 Termination Cycles4. During the data transfer cycles, the c_be_l lines indicate which byte lines are involved in each cycle. T

5–10 Host Bus Operation Termination CyclesFigure 5–7 shows the retried device (the host) releasing the bus. The host retries the last data transactio

Host Bus Operation 5–11 Termination Cycles5.5.2.1 21140A-Initiated TerminationA 21140A-initiated termination occurs when frame_l is deasserted and ird

xii 3–44 Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–393–45 Filtering Mode . .

5–12 Host Bus Operation Termination CyclesFigure 5–9 Master Abort5.5.2.2 Memory-Controller-Initiated TerminationThe memory controller or target can in

Host Bus Operation 5–13 Termination CyclesFigure 5–10 Target Abort 5.5.2.2.2 Target Disconnect TerminationThe 21140A terminates the bus transaction wh

5–14 Host Bus Operation Termination CyclesFigure 5–11 Target Disconnect5.5.2.2.3 Target RetryThe 21140A retries the bus transaction when the target as

Host Bus Operation 5–15 ParityFigure 5–12 Target Retry 5.6 ParityThe 21140A supports parity generation on all address, data, and command bits. Parity

5–16 Host Bus Operation ParkingFigure 5–13 Parity Operation5.7 ParkingParking in the PCI bus allows the central arbiter to pause any selected agent.

Network Interface Operation 6–1 6Network Interface OperationThis chapter describes the operation of the MII/SYM port and the serial (also referred to

6–2 Network Interface Operation MII/SYM Port• 100BASE-TX refers to the IEEE 802.3 PHY layer, which includes the 100BASE-X PCS and PMA together with th

Network Interface Operation 6–3 MII/SYM Port6.1.2.1 Signal StandardsTable 6–1 provides the standards that reference the MII/SYM port signal names with

6–4 Network Interface Operation MII/SYM Port6.1.2.2 Operating ModesThe 21140A implements the MII/SYM port signals (Table 6–1) to support the following

Network Interface Operation 6–5 MII/SYM PortThese functions include the following:– 4-bit and 5-bit decoding and encoding – Start-of-stream delimiter

xiii PrefacePurpose and AudienceThe DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller Hardware Reference Manual describes the operation of

6–6 Network Interface Operation Serial Port6.2 Serial PortThe serial port consists of seven signals that provide a conventional interface to the exist

Network Interface Operation 6–7 Media Access Control OperationDepending on the 21140A operating mode, a new frame transmission is defined as follows:•

6–8 Network Interface Operation Media Access Control Operation6.3.1.1 Ethernet and IEEE 802.3 FramesEthernet is the generic name for the network type.

Network Interface Operation 6–9 Media Access Control OperationTable 6–3 lists the possible values for the frame format. The values are expressed in h

6–10 Network Interface Operation Media Access Control Operation6.3.2 Ethernet Reception AddressingThe 21140A can be set up to recognize any one of the

Network Interface Operation 6–11 Media Access Control Operation6.3.3 Detailed Transmit OperationThis section describes the transmit operation in detai

6–12 Network Interface Operation Media Access Control OperationThe transmit encapsulation is performed by the transmit state machine, which delays the

Network Interface Operation 6–13 Media Access Control Operation6.3.3.4 CollisionA collision occurs when concurrent transmissions from two or more Ethe

6–14 Network Interface Operation Media Access Control Operation6.3.3.5 Terminating TransmissionA specific frame transmission is terminated by any of t

Network Interface Operation 6–15 Media Access Control Operation6.3.4 Detailed Receive OperationThis section describes the detailed receive operation a

xiv • Chapter 7, External Ports, describes the interface and operation of the MicroWire serial ROM, the boot ROM, the general-purpose port, and the ne

6–16 Network Interface Operation Media Access Control OperationThe 21140A allows any arbitrary preamble length. However, depending on the mode, there

Network Interface Operation 6–17 Media Access Control Operation6.3.4.3 Address MatchingEthernet addresses consist of two 6-byte fields: one field for

6–18 Network Interface Operation Media Access Control Operation• Collision—If a late collision occurs after the reception of 64 bytes of the packet, t

Network Interface Operation 6–19 Loopback Operations• Collision seen—A frame collision occurred after the 64 bytes following the start frame delimiter

6–20 Network Interface Operation Capture Effect–A Value-Added Feature2. Prepare appropriate transmit and receive descriptor lists in host memory. The

Network Interface Operation 6–21 Capture Effect–A Value-Added Feature6. If station A has another packet (data A2) ready to transmit while station B st

6–22 Network Interface Operation Power-Saving Modes6.6.2 Resolving Capture EffectThe 21140A generally resolves the capture effect by having the statio

Network Interface Operation 6–23 Power-Saving Modes6.7.1 Sleep Power-Saving ModeSleep mode can be activated when the 21140A is not being used (for exa

6–24 Network Interface Operation Jabber and Watchdog TimersWhen none of these conditions is true, the 21140A disables all its internal circuitries exc

External Ports 7–1 7External PortsThis chapter describes the interface and operation of the boot ROM, the MicroWire serial ROM, the general purpose po

Introduction 1–1 1IntroductionThis chapter provides a general description of the 21140A and its features. The chapter also includes an overview of t

7–2 External Ports Boot ROM and Serial ROM ConnectionFigure 7–1 Boot ROM, Serial ROM, and External Register ConnectionLJ03979B.AI421140Abr_ce_lsr_cssr

External Ports 7–3 Boot ROM Operations7.3 Boot ROM OperationsAccess to the boot ROM is done in two ways:• Byte access (read/write) using CSR9 and CSR1

7–4 External Ports Boot ROM OperationsFigure 7–2 Boot ROM Byte Read Cycle7.3.2 Byte WriteBefore performing a write operation, all the boot ROM entries

External Ports 7–5 Boot ROM OperationsFigure 7–3 Boot ROM Byte Write Cycle7.3.3 Dword ReadFigure 7–4 shows the Dword read cycle. The host initiates a

7–6 External Ports Serial ROM Operations9. The 21140A samples the data (byte 2).10. The 21140A drives br_a<1> to low, drives br_a<0> high,

External Ports 7–7 Serial ROM Operations7.4.1 Read OperationRead operations consist of three phases:1. Command phase—3 bits (binary code of 110)2. Add

7–8 External Ports Serial ROM OperationsFigure 7–5 Read Cycle (Page 1 of 2)LJ-04049.AI41.2.3.4.30 ns50 ns250 ns100 nsX = A0?NoYes15. 100 ns14. 250 ns1

External Ports 7–9 Serial ROM OperationsFigure 7–6 Read Cycle (Page 2 of 2)LJ-04050.AI419.EndAWrite CSR9<2:0> = 001#2Write CSR9<2:0> = 000

7–10 External Ports Serial ROM OperationsFigure 7–7 shows the read operation timing of the address and data.Figure 7–7 Read Operation7.4.2 Write Opera

External Ports 7–11 Serial ROM OperationsFigure 7–8 Write Cycle (Page 1 of 2)LJ-04052.AI4Write CSR9<2:0> = 000#2Write CSR9<2:0> = 001#2Wri

1–2 Introduction General Description1.1.1 21140A FeaturesAll 21140A devices have the following features:• Offers a single-chip Fast Ethernet controlle

7–12 External Ports Serial ROM OperationsFigure 7–9 Write Cycle (Page 2 of 2)LJ-04053.AI4Write CSR9<2:0> = 000#220. 250 nsWrite CSR9<2:0>

External Ports 7–13 External Register OperationFigure 7–10 shows the write operation timing of the address and data. The time period indicated by twp

7–14 External Ports General-Purpose Port Register (CSR12)7.6 General-Purpose Port Register (CSR12)The 21140A has an 8-pin general-purpose port that ca

Joint Test Action Group—Test Logic A–1 AJoint Test Action Group—Test LogicThis appendix describes the joint test action group (JTAG) test logic and t

A–2 Joint Test Action Group—Test Logic RegistersThese test pins operate in the same electrical environment as the 21140A PCI I/O buffers.The system ve

Joint Test Action Group—Test Logic A–3 Registers.A.2.2 Bypass RegisterThe bypass register is a 1-bit shift register that provides a single-bit serial

A–4 Joint Test Action Group—Test Logic RegistersA.2.3 Boundary-Scan RegisterThe JTAG boundary-scan register consists of cells located at the PCI and s

DNA CSMA/CD Counters and Events Support B–1 BDNA CSMA/CD Counters and Events SupportThis appendix describes the 21140A features that support the driv

B–2 DNA CSMA/CD Counters and Events SupportFrames sent, multiple collisions Driver must count the successfully transmitted frames when the collision c

DNA CSMA/CD Counters and Events Support B–31 As specified in the DNA Maintenance Operations (MOP) Functional Specification, Version T.4.0.0, 28 Januar

Introduction 1–3 Hardware Overview• Supports early interrupts on transmit and receive for improved performance• Implements low-power management with

Hash C Routine C–1 CHash C RoutineThis appendix provides examples of a C routine that generates the hash index for a given Ethernet address. The bit p

C–2 Hash C Routine 2. Big endian architecture Hash C routine.#include <stdio>unsigned HashIndex (char *Address); main (int argc, char *argv[]) {

Hash C Routine C–3 int Bit; int Shift; for (BytesLength=0; BytesLength<6; BytesLength++) { CurrentByte = Address[BytesLen

C–4 Hash C Routine } return Index;}

Support, Products, and Documentation D–1 DSupport, Products, and DocumentationTo view current product update and errata revision information, visit t

D–2 Support, Products, and Documentation DIGITAL Semiconductor ProductsTo order the DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller and

Support, Products, and Documentation D–3 DIGITAL Semiconductor DocumentationThe following table lists some of the available DIGITAL Semiconductor docu

Index–1 Index Numerics100BASE-FXimplementation, 6–2100BASE-Tdefinition, 6–1100BASE-T4implementation, 6–1100BASE-TXimplementation, 6–2100BASE-Ximplemen

1–4 Introduction Hardware Overview• TxM—Handles all CSMA/CD1 MAC2 transmit operations, and transfers data from transmit FIFO to the ENDEC for transmis

Index–2 CCapture effect2-0 backoff algorithm, 6–22definition, 6–20enable, 3–34example, 6–20resolution, 6–22sequence, 6–21special enable, 3–33Carrier-s

Index–3 DData communications, 4–1Descriptorerror, 6–19list addresses, 3–24missed frame counter, 3–44skip length, 3–21Descriptor list address registers

Index–4 Interpacket gapSee IPGInterrupt enable registerSee CSR7Interruptsabnormal, 3–27early receive, 3–28early receive enable, 3–42enabling, 3–40li

Index–5 OOperation mode registerSee CSR6PPacketsIPG, 6–19Paritydisable checking, 3–5error, 5–15detection, 3–4generation, 5–15software reset, 3–29stat

Index–6 Receive process, 4–35 to 4–37buffer unavailable, 3–28descriptor acquisition, 4–35frame processing, 4–35start, stop, 3–37state transitions, 4–3

Index–7 Transmitautomatic polling, 3–21buffer 1 address, 4–19buffer 2 address, 4–19collision counter, 4–15CRC disable, 4–17data buffer 1byte size, 4–1

Introduction 1–5 Hardware OverviewFigure 1–1 21140A Block DiagramRxFIFO321641411610 Mb/sSerial InterfacePhysical CodingSublayerMII/SYM InterfaceScram

Signal Descriptions 2–1 2Signal DescriptionsThis chapter provides the 21140A pinout, and a functional description of each of the signals.2.1 21140A Pi

2–2 Signal Descriptions 21140A PinoutFigure 2–1 21140A Pinout Diagram (Top View) LJ-04479.AI4vssvddmii_mdcmii_mdioncbr_a<1>br_a<0>br_ce_lb

Signal Descriptions 2–3 Signal Descriptions2.2 Signal DescriptionsTable 2–1 provides a functional description of each of the 21140A signals. The foll

2–4 Signal Descriptions Signal DescriptionsTable 2–1 Functional Description of 21140A Signals(Sheet 1 of 9) Signal TypePin Number Descriptionad<31:

Signal Descriptions 2–5 Signal Descriptionsc_be_l<3:0> I/O See Figure 2–1.Bits 0 through 3 of the bus command and byte enable lines. Bus comman

2–6 Signal Descriptions Signal Descriptionsint_l O/D 1 Interrupt request asserts when one of the appropriate bits of CSR5 sets and causes an interrupt

Signal Descriptions 2–7 Signal Descriptionsmii_err I 110 Receive error asserts when a data decoding error is detected by an external PHY device. This

Important NoticeAs of May 17, 1998, Digital Equipment Corporation’s StrongARM, PCI Bridge, and Networking component businesses, along with the chip f

2–8 Signal Descriptions Signal Descriptionsmii_txen O 125 Transmit enable signals that the transmit is active to an external PHY device. In PCS mode

Signal Descriptions 2–9 Signal Descriptionsreq_l O 8 Bus request is asserted by the 21140A to indicate to the bus arbiter that it wants to use the bus

2–10 Signal Descriptions Signal Descriptionssrl_rxd I 135 Receive data carries the input receive data from the external ENDEC. The incoming data s

Signal Descriptions 2–11 Signal Descriptionssym_txd<4> O 132 Transmit data together with the four transmit lines mii/sym_txd<3:0> provide

2–12 Signal Descriptions Signal Descriptionsvdd PSee Figure 2–1.A 3.3-V supply input voltage.vdd_clamp P 73 A 5-V reference for a 5-V signaling env

Registers 3–1 3RegistersThis chapter describes the configuration registers, and the command and status registers (CSRs) of the 21140A. The 21140A use

3–2 Registers Configuration Operation3.1.1 Configuration Register MappingTable 3–1 lists the definitions and addresses for the configuration registers

Registers 3–3 Configuration OperationTable 3–3 lists the access rules for the CFID register.3.1.2.2 Command and Status Configuration Register (CFCS–Of

3–4 Registers Configuration OperationFigure 3–2 CFCS Command and Status Configuration RegisterTable 3–4 CFCS Command and Status Configuration Register

Registers 3–5 Configuration Operation26:25 Status Device Select TimingIndicates the timing of the assertion of device select (devsel_l). These bits a

March 1998While DIGITAL believes the information included in this publication is correct as of the date of publication, it is subject to change withou

3–6 Registers Configuration OperationTable 3–5 lists the access rules for the CFCS register.3.1.2.3 Configuration Revision Register (CFRV–Offset 08H)T

Registers 3–7 Configuration OperationFigure 3–3 CFRV Configuration Revision Register Table 3–7 lists the revision and step numbers for each variant of

3–8 Registers Configuration OperationTable 3–8 lists the access rules for the CFRV register.3.1.2.4 Configuration Latency Timer Register (CFLT–Offset

Registers 3–9 Configuration OperationTable 3–10 lists the access rules for the CFLT register.Table 3–9 CFLT Configuration Latency Timer Register Descr

3–10 Registers Configuration Operation3.1.2.5 Configuration Base I/O Address Register (CBIO—Offset 10H)The CBIO register specifies the base I/O addres

Registers 3–11 Configuration Operation3.1.2.6 Configuration Base Memory Address Register (CBMA–Offset 14H) The CBMA register specifies the base memory

3–12 Registers Configuration Operation3.1.2.7 Subsystem ID Register (SSID–Offset 2CH)The SSID register is a read-only 32-bit register that is loaded f

Registers 3–13 Configuration Operation3.1.2.8 Expansion ROM Base Address Register (CBER–Offset 30H)The CBER register specifies the base address and pr

3–14 Registers Configuration Operation3.1.2.9 Configuration Interrupt Register (CFIT–Offset 3CH) The CFIT register is divided into two sections: the i

Registers 3–15 Configuration OperationTable 3–20 lists the access rules for the CFIT register. 3.1.2.10 Configuration Device and Driver Area Register

iii ContentsPreface1 Introduction1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–16 Registers Configuration OperationTable 3–22 lists the access rules for the CFDD register. Table 3–21 CFDD Configuration Driver Area Register D

Registers 3–17 CSR Operation3.2 CSR OperationThe 21140A CSRs are located in the host I/O or memory address space. The CSRs are quadword aligned, 32 b

3–18 Registers CSR OperationNote: Writing to CSR14 may cause UNPREDICTABLE behavior.3.2.2 Host CSRsThe 21140A implements 16 CSRs (CSR0 through CSR15),

Registers 3–19 CSR OperationTable 3–24 CSR0 Bus Mode Register Description(Sheet 1 of 3)Field Description24 WIE—Write and Invalidate EnableWhen set, th

3–20 Registers CSR Operation15:14 CAL—Cache AlignmentProgrammable address boundaries for data burst stop (Table 3–27). If the buffer is not aligned,

Registers 3–21 CSR OperationTable 3–25 defines the transmit automatic polling bits and lists the automatic polling intervals for MII 10/100-Mb/s and S

3–22 Registers CSR OperationTable 3–26 lists the CSR0 read and write access rules.Table 3–27 defines the cache address alignment bits. 3.2.2.2 Transmi

Registers 3–23 CSR OperationTable 3–29 lists the CSR1 read and write access rules.3.2.2.3 Receive Poll Demand Register (CSR2–Offset 10H)Figure 3–13 s

3–24 Registers CSR OperationTable 3–31 lists the access rules for CSR2.3.2.2.4 Descriptor List Address Registers (CSR3–Offset 18H and CSR4–Offset 20H)

Registers 3–25 CSR OperationTable 3–33 lists the access rules for CSR3.Figure 3–15 shows the CSR4 bit field and Table 3–34 describes the bit field.Fig

iv 3.2.2.1 Bus Mode Register (CSR0–Offset 00H). . . . . . . . . . . . . . . . . . . . . . . . . 3–183.2.2.2 Transmit Poll Demand Register (CSR1–Offset

3–26 Registers CSR Operation3.2.2.5 Status Register (CSR5–Offset 28H)The status register CSR5 contains all the status bits that the 21140A reports to

Registers 3–27 CSR OperationTable 3–36 CSR5 Status Register Description(Sheet 1 of 3)Field Description25:23 EB—Error Bits (Read Only)Indicates the typ

3–28 Registers CSR Operation14 ERI—Early Receive InterruptIndicates that the 21140A had filled the first data buffer of the packet. Receive interrupt

Registers 3–29 CSR OperationTable 3–37 lists the bit codes for the fatal bus error bits.1The only way to recover from a parity error is by setting sof

3–30 Registers CSR OperationTable 3–38 lists the bit codes for the transmit process state.Table 3–39 lists the bit codes for the receive process state

Registers 3–31 CSR OperationTable 3–40 lists the access rules for CSR5.3.2.2.6 Operation Mode Register (CSR6–Offset 30H)CSR6 establishes the receive a

3–32 Registers CSR OperationFigure 3–17 CSR6 Operating Mode Register 31 30 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8176543210LJ-05022.AI4RA

Registers 3–33 CSR OperationTable 3–41 CSR6 Operating Mode Register Description(Sheet 1 of 5)Field Description31 SC—Special Capture Effect EnableWhen

3–34 Registers CSR Operation19 HBD—Heartbeat DisableWhen set, the heartbeat signal quality (SQE) generator function is disabled. This bit should be s

Registers 3–35 CSR Operation13 ST—Start/Stop Transmission Command When set, the transmission process is placed in the running state, and the 21140A ch

v 4.3.5.3 Receive Process Suspended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–364.3.5.4 Receive Process State Transitions. .

3–36 Registers CSR Operation7 PM—Pass All Multicast When set, indicates that all the incoming frames with a multicast destination address (first bit i

Registers 3–37 CSR Operation2 HO—Hash-Only Filtering Mode (Read Only)When set, the 21140A operates in an imperfect address filtering mode for both phy

3–38 Registers CSR OperationTable 3–42 lists the threshold values in bytes.Table 3–43 lists the port and data rate selection. Table 3–42 Transmit Thre

Registers 3–39 CSR OperationTable 3–44 selects the 21140A loopback operation modes. 1Internal loopback is performed on the serial and MII/SYM ports.

3–40 Registers CSR Operation3.2.2.7 Interrupt Enable Register (CSR7–Offset 38H)The interrupt enable register (CSR7) enables the interrupts reported by

Registers 3–41 CSR OperationFigure 3–18 CSR7 Interrupt Enable Register 31 17 16 15 1314 111098765 3210LJ-05023.AI4NI - Normal Interrupt Summary Enable

3–42 Registers CSR OperationTable 3–47 CSR7 Interrupt Enable Register Description(Sheet 1 of 3)Field Description16 NI—Normal Interrupt Summary EnableW

Registers 3–43 CSR Operation13 FBE—Fatal Bus Error EnableWhen set together with abnormal interrupt summary enable (CSR7<15>) and fatal bus error

3–44 Registers CSR OperationTable 3–48 lists the access rules for CSR7.3.2.2.8 Missed Frames and Overflow Counter (CSR8–Offset 40H) Figure 3–19 shows

Registers 3–45 CSR OperationFigure 3–19 CSR8 Missed Frames and Overflow Counter Table 3–50 lists the access rules for CSR8.Table 3–49 CSR8 Missed Fram

vi 6.3.1.2 Ethernet Frame Format Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–86.3.2 Ethernet Reception Addressing . . . . .

3–46 Registers CSR Operation3.2.2.9 Boot ROM, Serial ROM, and MII Management Register (CSR9–Offset 48H)This register provides an interface to the boot

Registers 3–47 CSR Operation16 MDC—MII Management ClockMII management data clock (mii_mdc) is an output signal to the PHY. It is used as a timing ref

3–48 Registers CSR OperationTable 3–52 lists the access rules for CSR9.3.2.2.10 Boot ROM Programming Address Register (CSR10–Offset 50H)The boot ROM p

Registers 3–49 CSR OperationFigure 3–21 shows the CSR10 bit field and Table 3–53 describes the bit field. Figure 3–21 CSR10 Boot ROM Programming Add

3–50 Registers CSR OperationFigure 3–22 shows the CSR11 bit fields and Table 3–55 describes the bit fields.Figure 3–22 CSR11 General-Purpose Timer Reg

Registers 3–51 CSR OperationFigure 3–23 CSR12 General-Purpose Port Register Note:Refer to the 21140A application notes for the details regarding a par

3–52 Registers CSR OperationTable 3–58 lists the access rules for CSR12.3.2.2.13 Watchdog Timer Register (CSR1–Offset 78H)Figure 3–24 shows the CSR15

Registers 3–53 CSR OperationTable 3–59 CSR15 Watchdog Timer Register Description Field Description5 RWR—Receive Watchd

3–54 Registers CSR OperationTable 3–60 lists the access rules for CSR15. Table 3–60 CSR15 Access RulesCategory DescriptionValue after reset FFFFFEC8HR

Host Communication 4–1 4Host CommunicationThis chapter describes descriptor lists and data buffers, which are collectively called the host communicati

vii A Joint Test Action Group—Test LogicA.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Host Communication Descriptor Lists and Data BuffersA data buffer consists of either an entire frame or part of a frame, but it cannot exceed a si

Host Communication 4–3 Descriptor Lists and Data Buffers4.2.1 Receive DescriptorsFigure 4–2 shows the receive descriptor format.Note: Descriptors and

4–4 Host Communication Descriptor Lists and Data BuffersFigure 4–3 RDES0 Receive Descriptor 0 31302928272625242322212019181716151413121110987654 2310L

Host Communication 4–5 Descriptor Lists and Data BuffersTable 4–1 RDES0 Receive Descriptor 0 Description(Sheet 1 of 4)Field Description31 OWN—Own Bit

4–6 Host Communication Descriptor Lists and Data Buffers13:12 DT—Data Type Indicates the type of frame the buffer contains:00—Serial received frame.01

Host Communication 4–7 Descriptor Lists and Data Buffers7 TL—Frame Too LongWhen set, indicates that the frame length exceeds the maximum Ethernet-spec

4–8 Host Communication Descriptor Lists and Data Buffers4.2.1.2 Receive Descriptor 1 (RDES1)Figure 4–4 shows the RDES1 bit fields and Table 4–2 descri

Host Communication 4–9 Descriptor Lists and Data Buffers4.2.1.3 Receive Descriptor 2 (RDES2)Figure 4–5 shows the RDES2 bit field and Table 4–3 describ

4–10 Host Communication Descriptor Lists and Data Buffers4.2.1.4 Receive Descriptor 3 (RDES3)Figure 4–6 shows the RDES3 bit field and Table 4–4 descri

Host Communication 4–11 Descriptor Lists and Data BuffersList of table abbreviationsRF—Runt frame (RDES0<11>)CS—Collision seen (RDES0<6>)